/[gxemul]/trunk/src/cpus/cpu_avr_instr.c
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Contents of /trunk/src/cpus/cpu_avr_instr.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9011 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============
1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_avr_instr.c,v 1.4 2005/11/06 22:41:12 debug Exp $
29 *
30 * Atmel AVR (8-bit) instructions.
31 *
32 * Individual functions should keep track of cpu->n_translated_instrs.
33 * (n_translated_instrs is automatically increased by 1 for each function
34 * call. If no instruction was executed, then it should be decreased. If, say,
35 * 4 instructions were combined into one function and executed, then it should
36 * be increased by 3.)
37 */
38
39
40 /*****************************************************************************/
41
42
43 /*
44 * nop: Do nothing.
45 */
46 X(nop)
47 {
48 }
49
50
51 /*
52 * clX: Clear an sreg bit.
53 */
54 X(clc) { cpu->cd.avr.sreg &= ~AVR_SREG_C; }
55 X(clz) { cpu->cd.avr.sreg &= ~AVR_SREG_Z; }
56 X(cln) { cpu->cd.avr.sreg &= ~AVR_SREG_N; }
57 X(clv) { cpu->cd.avr.sreg &= ~AVR_SREG_V; }
58 X(cls) { cpu->cd.avr.sreg &= ~AVR_SREG_S; }
59 X(clh) { cpu->cd.avr.sreg &= ~AVR_SREG_H; }
60 X(clt) { cpu->cd.avr.sreg &= ~AVR_SREG_T; }
61 X(cli) { cpu->cd.avr.sreg &= ~AVR_SREG_I; }
62
63
64 /*
65 * ldi: Load immediate.
66 *
67 * arg[0]: ptr to register
68 * arg[1]: byte value
69 */
70 X(ldi)
71 {
72 *(uint8_t *)(ic->arg[0]) = ic->arg[1];
73 }
74
75
76 /*
77 * mov: Copy register.
78 *
79 * arg[0]: ptr to rr
80 * arg[1]: ptr to rd
81 */
82 X(mov)
83 {
84 *(uint8_t *)(ic->arg[1]) = *(uint8_t *)(ic->arg[0]);
85 }
86
87
88 /*
89 * rjmp: Relative jump.
90 *
91 * arg[0]: relative offset
92 */
93 X(rjmp)
94 {
95 uint32_t low_pc;
96
97 cpu->cd.avr.extra_cycles ++;
98
99 /* Calculate new PC from the next instruction + arg[0] */
100 low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page) /
101 sizeof(struct avr_instr_call);
102 cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1)
103 << AVR_INSTR_ALIGNMENT_SHIFT);
104 cpu->pc += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
105 cpu->pc += (int32_t)ic->arg[0];
106
107 /* Find the new physical page and update the translation pointers: */
108 avr_pc_to_pointers(cpu);
109 }
110
111
112 /*
113 * rjmp_samepage: Relative jump (to within the same translated page).
114 *
115 * arg[0] = pointer to new avr_instr_call
116 */
117 X(rjmp_samepage)
118 {
119 cpu->cd.avr.extra_cycles ++;
120 cpu->cd.avr.next_ic = (struct avr_instr_call *) ic->arg[0];
121 }
122
123
124 /*
125 * seX: Set an sreg bit.
126 */
127 X(sec) { cpu->cd.avr.sreg |= AVR_SREG_C; }
128 X(sez) { cpu->cd.avr.sreg |= AVR_SREG_Z; }
129 X(sen) { cpu->cd.avr.sreg |= AVR_SREG_N; }
130 X(sev) { cpu->cd.avr.sreg |= AVR_SREG_V; }
131 X(ses) { cpu->cd.avr.sreg |= AVR_SREG_S; }
132 X(seh) { cpu->cd.avr.sreg |= AVR_SREG_H; }
133 X(set) { cpu->cd.avr.sreg |= AVR_SREG_T; }
134 X(sei) { cpu->cd.avr.sreg |= AVR_SREG_I; }
135
136
137 /*
138 * swap: Swap nibbles.
139 *
140 * arg[0]: ptr to rd
141 */
142 X(swap)
143 {
144 uint8_t x = *(uint8_t *)(ic->arg[0]);
145 *(uint8_t *)(ic->arg[0]) = (x >> 4) | (x << 4);
146 }
147
148
149 /*****************************************************************************/
150
151
152 X(end_of_page)
153 {
154 /* Update the PC: (offset 0, but on the next page) */
155 cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1) << 1);
156 cpu->pc += (AVR_IC_ENTRIES_PER_PAGE << 1);
157
158 /* Find the new physical page and update the translation pointers: */
159 avr_pc_to_pointers(cpu);
160
161 /* end_of_page doesn't count as an executed instruction: */
162 cpu->n_translated_instrs --;
163 }
164
165
166 /*****************************************************************************/
167
168
169 /*
170 * avr_combine_instructions():
171 *
172 * Combine two or more instructions, if possible, into a single function call.
173 */
174 void avr_combine_instructions(struct cpu *cpu, struct avr_instr_call *ic,
175 uint32_t addr)
176 {
177 int n_back;
178 n_back = (addr >> 1) & (AVR_IC_ENTRIES_PER_PAGE-1);
179
180 if (n_back >= 1) {
181 /* TODO */
182 }
183
184 /* TODO: Combine forward as well */
185 }
186
187
188 /*****************************************************************************/
189
190
191 /*
192 * avr_instr_to_be_translated():
193 *
194 * Translate an instruction word into an avr_instr_call. ic is filled in with
195 * valid data for the translated instruction, or a "nothing" instruction if
196 * there was a translation failure. The newly translated instruction is then
197 * executed.
198 */
199 X(to_be_translated)
200 {
201 int addr, low_pc, rd, rr, main_opcode;
202 uint16_t iword;
203 unsigned char *page;
204 unsigned char ib[2];
205 void (*samepage_function)(struct cpu *, struct avr_instr_call *);
206
207 /* Figure out the (virtual) address of the instruction: */
208 low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page)
209 / sizeof(struct avr_instr_call);
210 addr = cpu->pc & ~((AVR_IC_ENTRIES_PER_PAGE-1) <<
211 AVR_INSTR_ALIGNMENT_SHIFT);
212 addr += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
213 cpu->pc = addr;
214 addr &= ~((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
215
216 addr &= cpu->cd.avr.pc_mask;
217
218 /* Read the instruction word from memory: */
219 page = cpu->cd.avr.host_load[addr >> 12];
220
221 if (page != NULL) {
222 /* fatal("TRANSLATION HIT!\n"); */
223 memcpy(ib, page + (addr & 0xfff), sizeof(ib));
224 } else {
225 /* fatal("TRANSLATION MISS!\n"); */
226 if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
227 sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
228 fatal("to_be_translated(): "
229 "read failed: TODO\n");
230 goto bad;
231 }
232 }
233
234 iword = *((uint16_t *)&ib[0]);
235
236 #ifdef HOST_BIG_ENDIAN
237 iword = ((iword & 0xff) << 8) |
238 ((iword & 0xff00) >> 8);
239 #endif
240
241
242 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
243 #include "cpu_dyntrans.c"
244 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
245
246
247 /*
248 * Translate the instruction:
249 */
250 main_opcode = iword >> 12;
251
252 switch (main_opcode) {
253
254 case 0x0:
255 if (iword == 0x0000) {
256 ic->f = instr(nop);
257 break;
258 }
259 goto bad;
260
261 case 0x2:
262 if ((iword & 0xfc00) == 0x2c00) {
263 rd = (iword & 0x1f0) >> 4;
264 rr = ((iword & 0x200) >> 5) | (iword & 0xf);
265 ic->f = instr(mov);
266 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rr]);
267 ic->arg[1] = (size_t)(&cpu->cd.avr.r[rd]);
268 break;
269 }
270 goto bad;
271
272 case 0x9:
273 if ((iword & 0xfe0f) == 0x9402) {
274 rd = (iword >> 4) & 31;
275 ic->f = instr(swap);
276 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
277 break;
278 }
279 if ((iword & 0xff8f) == 0x9408) {
280 switch ((iword >> 4) & 7) {
281 case 0: ic->f = instr(sec); break;
282 case 1: ic->f = instr(sez); break;
283 case 2: ic->f = instr(sen); break;
284 case 3: ic->f = instr(sev); break;
285 case 4: ic->f = instr(ses); break;
286 case 5: ic->f = instr(seh); break;
287 case 6: ic->f = instr(set); break;
288 case 7: ic->f = instr(sei); break;
289 }
290 break;
291 }
292 if ((iword & 0xff8f) == 0x9488) {
293 switch ((iword >> 4) & 7) {
294 case 0: ic->f = instr(clc); break;
295 case 1: ic->f = instr(clz); break;
296 case 2: ic->f = instr(cln); break;
297 case 3: ic->f = instr(clv); break;
298 case 4: ic->f = instr(cls); break;
299 case 5: ic->f = instr(clh); break;
300 case 6: ic->f = instr(clt); break;
301 case 7: ic->f = instr(cli); break;
302 }
303 break;
304 }
305 goto bad;
306
307 case 0xc:
308 ic->f = instr(rjmp);
309 samepage_function = instr(rjmp_samepage);
310 ic->arg[0] = (((int16_t)((iword & 0x0fff) << 4)) >> 3) + 2;
311 /* Special case: branch within the same page: */
312 {
313 uint32_t mask_within_page =
314 ((AVR_IC_ENTRIES_PER_PAGE-1) <<
315 AVR_INSTR_ALIGNMENT_SHIFT) |
316 ((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
317 uint32_t old_pc = addr;
318 uint32_t new_pc = old_pc + (int32_t)ic->arg[0];
319 if ((old_pc & ~mask_within_page) ==
320 (new_pc & ~mask_within_page)) {
321 ic->f = samepage_function;
322 ic->arg[0] = (size_t) (
323 cpu->cd.avr.cur_ic_page +
324 ((new_pc & mask_within_page) >>
325 AVR_INSTR_ALIGNMENT_SHIFT));
326 }
327 }
328 break;
329
330 case 0xe:
331 rd = ((iword >> 4) & 0xf) + 16;
332 ic->f = instr(ldi);
333 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
334 ic->arg[1] = ((iword >> 4) & 0xf0) | (iword & 0xf);
335 break;
336
337 default:goto bad;
338 }
339
340
341 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
342 #include "cpu_dyntrans.c"
343 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
344 }
345
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