/[gxemul]/trunk/src/cpus/cpu_avr_instr.c
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Contents of /trunk/src/cpus/cpu_avr_instr.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 9271 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_avr_instr.c,v 1.3 2005/09/17 22:34:52 debug Exp $
29 *
30 * Atmel AVR (8-bit) instructions.
31 *
32 * Individual functions should keep track of cpu->n_translated_instrs. Since
33 * AVR uses variable length instructions, cpu->cd.avr.next_ic must also be
34 * increased by the number of "instruction slots" that were executed. (I.e.
35 * if an instruction occupying 6 bytes was executed, then next_ic should be
36 * increased by 3.)
37 *
38 * (n_translated_instrs is automatically increased by 1 for each function
39 * call. If no instruction was executed, then it should be decreased. If, say,
40 * 4 instructions were combined into one function and executed, then it should
41 * be increased by 3.)
42 */
43
44
45 /*****************************************************************************/
46
47
48 /*
49 * nop: Do nothing.
50 */
51 X(nop)
52 {
53 }
54
55
56 /*
57 * clX: Clear an sreg bit.
58 */
59 X(clc) { cpu->cd.avr.sreg &= ~AVR_SREG_C; }
60 X(clz) { cpu->cd.avr.sreg &= ~AVR_SREG_Z; }
61 X(cln) { cpu->cd.avr.sreg &= ~AVR_SREG_N; }
62 X(clv) { cpu->cd.avr.sreg &= ~AVR_SREG_V; }
63 X(cls) { cpu->cd.avr.sreg &= ~AVR_SREG_S; }
64 X(clh) { cpu->cd.avr.sreg &= ~AVR_SREG_H; }
65 X(clt) { cpu->cd.avr.sreg &= ~AVR_SREG_T; }
66 X(cli) { cpu->cd.avr.sreg &= ~AVR_SREG_I; }
67
68
69 /*
70 * ldi: Load immediate.
71 *
72 * arg[0]: ptr to register
73 * arg[1]: byte value
74 */
75 X(ldi)
76 {
77 *(uint8_t *)(ic->arg[0]) = ic->arg[1];
78 }
79
80
81 /*
82 * mov: Copy register.
83 *
84 * arg[0]: ptr to rr
85 * arg[1]: ptr to rd
86 */
87 X(mov)
88 {
89 *(uint8_t *)(ic->arg[1]) = *(uint8_t *)(ic->arg[0]);
90 }
91
92
93 /*
94 * rjmp: Relative jump.
95 *
96 * arg[0]: relative offset
97 */
98 X(rjmp)
99 {
100 uint32_t low_pc;
101
102 cpu->cd.avr.extra_cycles ++;
103
104 /* Calculate new PC from the next instruction + arg[0] */
105 low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page) /
106 sizeof(struct avr_instr_call);
107 cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1)
108 << AVR_INSTR_ALIGNMENT_SHIFT);
109 cpu->pc += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
110 cpu->pc += (int32_t)ic->arg[0];
111
112 /* Find the new physical page and update the translation pointers: */
113 avr_pc_to_pointers(cpu);
114 }
115
116
117 /*
118 * rjmp_samepage: Relative jump (to within the same translated page).
119 *
120 * arg[0] = pointer to new avr_instr_call
121 */
122 X(rjmp_samepage)
123 {
124 cpu->cd.avr.extra_cycles ++;
125 cpu->cd.avr.next_ic = (struct avr_instr_call *) ic->arg[0];
126 }
127
128
129 /*
130 * seX: Set an sreg bit.
131 */
132 X(sec) { cpu->cd.avr.sreg |= AVR_SREG_C; }
133 X(sez) { cpu->cd.avr.sreg |= AVR_SREG_Z; }
134 X(sen) { cpu->cd.avr.sreg |= AVR_SREG_N; }
135 X(sev) { cpu->cd.avr.sreg |= AVR_SREG_V; }
136 X(ses) { cpu->cd.avr.sreg |= AVR_SREG_S; }
137 X(seh) { cpu->cd.avr.sreg |= AVR_SREG_H; }
138 X(set) { cpu->cd.avr.sreg |= AVR_SREG_T; }
139 X(sei) { cpu->cd.avr.sreg |= AVR_SREG_I; }
140
141
142 /*
143 * swap: Swap nibbles.
144 *
145 * arg[0]: ptr to rd
146 */
147 X(swap)
148 {
149 uint8_t x = *(uint8_t *)(ic->arg[0]);
150 *(uint8_t *)(ic->arg[0]) = (x >> 4) | (x << 4);
151 }
152
153
154 /*****************************************************************************/
155
156
157 X(end_of_page)
158 {
159 /* Update the PC: (offset 0, but on the next page) */
160 cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1) << 1);
161 cpu->pc += (AVR_IC_ENTRIES_PER_PAGE << 1);
162
163 /* Find the new physical page and update the translation pointers: */
164 avr_pc_to_pointers(cpu);
165
166 /* end_of_page doesn't count as an executed instruction: */
167 cpu->n_translated_instrs --;
168 }
169
170
171 /*****************************************************************************/
172
173
174 /*
175 * avr_combine_instructions():
176 *
177 * Combine two or more instructions, if possible, into a single function call.
178 */
179 void avr_combine_instructions(struct cpu *cpu, struct avr_instr_call *ic,
180 uint32_t addr)
181 {
182 int n_back;
183 n_back = (addr >> 1) & (AVR_IC_ENTRIES_PER_PAGE-1);
184
185 if (n_back >= 1) {
186 /* TODO */
187 }
188
189 /* TODO: Combine forward as well */
190 }
191
192
193 /*****************************************************************************/
194
195
196 /*
197 * avr_instr_to_be_translated():
198 *
199 * Translate an instruction word into an avr_instr_call. ic is filled in with
200 * valid data for the translated instruction, or a "nothing" instruction if
201 * there was a translation failure. The newly translated instruction is then
202 * executed.
203 */
204 X(to_be_translated)
205 {
206 int addr, low_pc, rd, rr, main_opcode;
207 uint16_t iword;
208 unsigned char *page;
209 unsigned char ib[2];
210 void (*samepage_function)(struct cpu *, struct avr_instr_call *);
211
212 /* Figure out the (virtual) address of the instruction: */
213 low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page)
214 / sizeof(struct avr_instr_call);
215 addr = cpu->pc & ~((AVR_IC_ENTRIES_PER_PAGE-1) <<
216 AVR_INSTR_ALIGNMENT_SHIFT);
217 addr += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
218 cpu->pc = addr;
219 addr &= ~((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
220
221 addr &= cpu->cd.avr.pc_mask;
222
223 /* Read the instruction word from memory: */
224 page = cpu->cd.avr.host_load[addr >> 12];
225
226 if (page != NULL) {
227 /* fatal("TRANSLATION HIT!\n"); */
228 memcpy(ib, page + (addr & 0xfff), sizeof(ib));
229 } else {
230 /* fatal("TRANSLATION MISS!\n"); */
231 if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
232 sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
233 fatal("to_be_translated(): "
234 "read failed: TODO\n");
235 goto bad;
236 }
237 }
238
239 iword = *((uint16_t *)&ib[0]);
240
241 #ifdef HOST_BIG_ENDIAN
242 iword = ((iword & 0xff) << 8) |
243 ((iword & 0xff00) >> 8);
244 #endif
245
246
247 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
248 #include "cpu_dyntrans.c"
249 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
250
251
252 /*
253 * Translate the instruction:
254 */
255 main_opcode = iword >> 12;
256
257 switch (main_opcode) {
258
259 case 0x0:
260 if (iword == 0x0000) {
261 ic->f = instr(nop);
262 break;
263 }
264 goto bad;
265
266 case 0x2:
267 if ((iword & 0xfc00) == 0x2c00) {
268 rd = (iword & 0x1f0) >> 4;
269 rr = ((iword & 0x200) >> 5) | (iword & 0xf);
270 ic->f = instr(mov);
271 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rr]);
272 ic->arg[1] = (size_t)(&cpu->cd.avr.r[rd]);
273 break;
274 }
275 goto bad;
276
277 case 0x9:
278 if ((iword & 0xfe0f) == 0x9402) {
279 rd = (iword >> 4) & 31;
280 ic->f = instr(swap);
281 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
282 break;
283 }
284 if ((iword & 0xff8f) == 0x9408) {
285 switch ((iword >> 4) & 7) {
286 case 0: ic->f = instr(sec); break;
287 case 1: ic->f = instr(sez); break;
288 case 2: ic->f = instr(sen); break;
289 case 3: ic->f = instr(sev); break;
290 case 4: ic->f = instr(ses); break;
291 case 5: ic->f = instr(seh); break;
292 case 6: ic->f = instr(set); break;
293 case 7: ic->f = instr(sei); break;
294 }
295 break;
296 }
297 if ((iword & 0xff8f) == 0x9488) {
298 switch ((iword >> 4) & 7) {
299 case 0: ic->f = instr(clc); break;
300 case 1: ic->f = instr(clz); break;
301 case 2: ic->f = instr(cln); break;
302 case 3: ic->f = instr(clv); break;
303 case 4: ic->f = instr(cls); break;
304 case 5: ic->f = instr(clh); break;
305 case 6: ic->f = instr(clt); break;
306 case 7: ic->f = instr(cli); break;
307 }
308 break;
309 }
310 goto bad;
311
312 case 0xc:
313 ic->f = instr(rjmp);
314 samepage_function = instr(rjmp_samepage);
315 ic->arg[0] = (((int16_t)((iword & 0x0fff) << 4)) >> 3) + 2;
316 /* Special case: branch within the same page: */
317 {
318 uint32_t mask_within_page =
319 ((AVR_IC_ENTRIES_PER_PAGE-1) <<
320 AVR_INSTR_ALIGNMENT_SHIFT) |
321 ((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
322 uint32_t old_pc = addr;
323 uint32_t new_pc = old_pc + (int32_t)ic->arg[0];
324 if ((old_pc & ~mask_within_page) ==
325 (new_pc & ~mask_within_page)) {
326 ic->f = samepage_function;
327 ic->arg[0] = (size_t) (
328 cpu->cd.avr.cur_ic_page +
329 ((new_pc & mask_within_page) >>
330 AVR_INSTR_ALIGNMENT_SHIFT));
331 }
332 }
333 break;
334
335 case 0xe:
336 rd = ((iword >> 4) & 0xf) + 16;
337 ic->f = instr(ldi);
338 ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
339 ic->arg[1] = ((iword >> 4) & 0xf0) | (iword & 0xf);
340 break;
341
342 default:goto bad;
343 }
344
345
346 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
347 #include "cpu_dyntrans.c"
348 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
349 }
350

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