/[gxemul]/trunk/src/cpus/cpu_avr_instr.c
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Annotation of /trunk/src/cpus/cpu_avr_instr.c

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Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 dpavlin 14 /*
2 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: cpu_avr_instr.c,v 1.6 2006/02/09 22:40:27 debug Exp $
29 dpavlin 14 *
30     * Atmel AVR (8-bit) instructions.
31     *
32 dpavlin 20 * Individual functions should keep track of cpu->n_translated_instrs.
33 dpavlin 14 * (n_translated_instrs is automatically increased by 1 for each function
34     * call. If no instruction was executed, then it should be decreased. If, say,
35     * 4 instructions were combined into one function and executed, then it should
36     * be increased by 3.)
37     */
38    
39    
40     /*****************************************************************************/
41    
42    
43     /*
44     * nop: Do nothing.
45     */
46     X(nop)
47     {
48     }
49    
50    
51     /*
52     * clX: Clear an sreg bit.
53     */
54     X(clc) { cpu->cd.avr.sreg &= ~AVR_SREG_C; }
55     X(clz) { cpu->cd.avr.sreg &= ~AVR_SREG_Z; }
56     X(cln) { cpu->cd.avr.sreg &= ~AVR_SREG_N; }
57     X(clv) { cpu->cd.avr.sreg &= ~AVR_SREG_V; }
58     X(cls) { cpu->cd.avr.sreg &= ~AVR_SREG_S; }
59     X(clh) { cpu->cd.avr.sreg &= ~AVR_SREG_H; }
60     X(clt) { cpu->cd.avr.sreg &= ~AVR_SREG_T; }
61     X(cli) { cpu->cd.avr.sreg &= ~AVR_SREG_I; }
62    
63    
64     /*
65     * ldi: Load immediate.
66     *
67     * arg[0]: ptr to register
68     * arg[1]: byte value
69     */
70     X(ldi)
71     {
72     *(uint8_t *)(ic->arg[0]) = ic->arg[1];
73     }
74    
75    
76     /*
77     * mov: Copy register.
78     *
79     * arg[0]: ptr to rr
80     * arg[1]: ptr to rd
81     */
82     X(mov)
83     {
84     *(uint8_t *)(ic->arg[1]) = *(uint8_t *)(ic->arg[0]);
85     }
86    
87    
88     /*
89     * rjmp: Relative jump.
90     *
91     * arg[0]: relative offset
92     */
93     X(rjmp)
94     {
95     uint32_t low_pc;
96    
97     cpu->cd.avr.extra_cycles ++;
98    
99     /* Calculate new PC from the next instruction + arg[0] */
100     low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page) /
101     sizeof(struct avr_instr_call);
102     cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1)
103     << AVR_INSTR_ALIGNMENT_SHIFT);
104     cpu->pc += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
105     cpu->pc += (int32_t)ic->arg[0];
106    
107     /* Find the new physical page and update the translation pointers: */
108     avr_pc_to_pointers(cpu);
109     }
110    
111    
112     /*
113     * rjmp_samepage: Relative jump (to within the same translated page).
114     *
115     * arg[0] = pointer to new avr_instr_call
116     */
117     X(rjmp_samepage)
118     {
119     cpu->cd.avr.extra_cycles ++;
120     cpu->cd.avr.next_ic = (struct avr_instr_call *) ic->arg[0];
121     }
122    
123    
124     /*
125     * seX: Set an sreg bit.
126     */
127     X(sec) { cpu->cd.avr.sreg |= AVR_SREG_C; }
128     X(sez) { cpu->cd.avr.sreg |= AVR_SREG_Z; }
129     X(sen) { cpu->cd.avr.sreg |= AVR_SREG_N; }
130     X(sev) { cpu->cd.avr.sreg |= AVR_SREG_V; }
131     X(ses) { cpu->cd.avr.sreg |= AVR_SREG_S; }
132     X(seh) { cpu->cd.avr.sreg |= AVR_SREG_H; }
133     X(set) { cpu->cd.avr.sreg |= AVR_SREG_T; }
134     X(sei) { cpu->cd.avr.sreg |= AVR_SREG_I; }
135    
136    
137     /*
138     * swap: Swap nibbles.
139     *
140     * arg[0]: ptr to rd
141     */
142     X(swap)
143     {
144     uint8_t x = *(uint8_t *)(ic->arg[0]);
145     *(uint8_t *)(ic->arg[0]) = (x >> 4) | (x << 4);
146     }
147    
148    
149     /*****************************************************************************/
150    
151    
152     X(end_of_page)
153     {
154     /* Update the PC: (offset 0, but on the next page) */
155     cpu->pc &= ~((AVR_IC_ENTRIES_PER_PAGE-1) << 1);
156     cpu->pc += (AVR_IC_ENTRIES_PER_PAGE << 1);
157    
158     /* Find the new physical page and update the translation pointers: */
159     avr_pc_to_pointers(cpu);
160    
161     /* end_of_page doesn't count as an executed instruction: */
162     cpu->n_translated_instrs --;
163     }
164    
165    
166     /*****************************************************************************/
167    
168    
169     /*
170     * avr_combine_instructions():
171     *
172     * Combine two or more instructions, if possible, into a single function call.
173     */
174     void avr_combine_instructions(struct cpu *cpu, struct avr_instr_call *ic,
175     uint32_t addr)
176     {
177     int n_back;
178     n_back = (addr >> 1) & (AVR_IC_ENTRIES_PER_PAGE-1);
179    
180     if (n_back >= 1) {
181     /* TODO */
182     }
183    
184     /* TODO: Combine forward as well */
185     }
186    
187    
188     /*****************************************************************************/
189    
190    
191     /*
192     * avr_instr_to_be_translated():
193     *
194     * Translate an instruction word into an avr_instr_call. ic is filled in with
195     * valid data for the translated instruction, or a "nothing" instruction if
196     * there was a translation failure. The newly translated instruction is then
197     * executed.
198     */
199     X(to_be_translated)
200     {
201     int addr, low_pc, rd, rr, main_opcode;
202 dpavlin 22 #ifdef DYNTRANS_BACKEND
203     int simple = 0;
204     #endif
205 dpavlin 14 uint16_t iword;
206     unsigned char *page;
207     unsigned char ib[2];
208     void (*samepage_function)(struct cpu *, struct avr_instr_call *);
209    
210     /* Figure out the (virtual) address of the instruction: */
211     low_pc = ((size_t)ic - (size_t)cpu->cd.avr.cur_ic_page)
212     / sizeof(struct avr_instr_call);
213     addr = cpu->pc & ~((AVR_IC_ENTRIES_PER_PAGE-1) <<
214     AVR_INSTR_ALIGNMENT_SHIFT);
215     addr += (low_pc << AVR_INSTR_ALIGNMENT_SHIFT);
216     cpu->pc = addr;
217     addr &= ~((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
218    
219     addr &= cpu->cd.avr.pc_mask;
220    
221     /* Read the instruction word from memory: */
222     page = cpu->cd.avr.host_load[addr >> 12];
223    
224     if (page != NULL) {
225     /* fatal("TRANSLATION HIT!\n"); */
226     memcpy(ib, page + (addr & 0xfff), sizeof(ib));
227     } else {
228     /* fatal("TRANSLATION MISS!\n"); */
229     if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
230     sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
231     fatal("to_be_translated(): "
232     "read failed: TODO\n");
233     goto bad;
234     }
235     }
236    
237     iword = *((uint16_t *)&ib[0]);
238    
239     #ifdef HOST_BIG_ENDIAN
240     iword = ((iword & 0xff) << 8) |
241     ((iword & 0xff00) >> 8);
242     #endif
243    
244    
245     #define DYNTRANS_TO_BE_TRANSLATED_HEAD
246     #include "cpu_dyntrans.c"
247     #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
248    
249    
250     /*
251     * Translate the instruction:
252     */
253     main_opcode = iword >> 12;
254    
255     switch (main_opcode) {
256    
257     case 0x0:
258     if (iword == 0x0000) {
259     ic->f = instr(nop);
260     break;
261     }
262     goto bad;
263    
264     case 0x2:
265     if ((iword & 0xfc00) == 0x2c00) {
266     rd = (iword & 0x1f0) >> 4;
267     rr = ((iword & 0x200) >> 5) | (iword & 0xf);
268     ic->f = instr(mov);
269     ic->arg[0] = (size_t)(&cpu->cd.avr.r[rr]);
270     ic->arg[1] = (size_t)(&cpu->cd.avr.r[rd]);
271     break;
272     }
273     goto bad;
274    
275     case 0x9:
276     if ((iword & 0xfe0f) == 0x9402) {
277     rd = (iword >> 4) & 31;
278     ic->f = instr(swap);
279     ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
280     break;
281     }
282     if ((iword & 0xff8f) == 0x9408) {
283     switch ((iword >> 4) & 7) {
284     case 0: ic->f = instr(sec); break;
285     case 1: ic->f = instr(sez); break;
286     case 2: ic->f = instr(sen); break;
287     case 3: ic->f = instr(sev); break;
288     case 4: ic->f = instr(ses); break;
289     case 5: ic->f = instr(seh); break;
290     case 6: ic->f = instr(set); break;
291     case 7: ic->f = instr(sei); break;
292     }
293     break;
294     }
295     if ((iword & 0xff8f) == 0x9488) {
296     switch ((iword >> 4) & 7) {
297     case 0: ic->f = instr(clc); break;
298     case 1: ic->f = instr(clz); break;
299     case 2: ic->f = instr(cln); break;
300     case 3: ic->f = instr(clv); break;
301     case 4: ic->f = instr(cls); break;
302     case 5: ic->f = instr(clh); break;
303     case 6: ic->f = instr(clt); break;
304     case 7: ic->f = instr(cli); break;
305     }
306     break;
307     }
308     goto bad;
309    
310     case 0xc:
311     ic->f = instr(rjmp);
312     samepage_function = instr(rjmp_samepage);
313     ic->arg[0] = (((int16_t)((iword & 0x0fff) << 4)) >> 3) + 2;
314     /* Special case: branch within the same page: */
315     {
316     uint32_t mask_within_page =
317     ((AVR_IC_ENTRIES_PER_PAGE-1) <<
318     AVR_INSTR_ALIGNMENT_SHIFT) |
319     ((1 << AVR_INSTR_ALIGNMENT_SHIFT) - 1);
320     uint32_t old_pc = addr;
321     uint32_t new_pc = old_pc + (int32_t)ic->arg[0];
322     if ((old_pc & ~mask_within_page) ==
323     (new_pc & ~mask_within_page)) {
324     ic->f = samepage_function;
325     ic->arg[0] = (size_t) (
326     cpu->cd.avr.cur_ic_page +
327     ((new_pc & mask_within_page) >>
328     AVR_INSTR_ALIGNMENT_SHIFT));
329     }
330     }
331     break;
332    
333     case 0xe:
334     rd = ((iword >> 4) & 0xf) + 16;
335     ic->f = instr(ldi);
336     ic->arg[0] = (size_t)(&cpu->cd.avr.r[rd]);
337     ic->arg[1] = ((iword >> 4) & 0xf0) | (iword & 0xf);
338     break;
339    
340     default:goto bad;
341     }
342    
343    
344     #define DYNTRANS_TO_BE_TRANSLATED_TAIL
345     #include "cpu_dyntrans.c"
346     #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
347     }
348    
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