/[gxemul]/trunk/src/cpus/cpu_avr.c
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Contents of /trunk/src/cpus/cpu_avr.c

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Revision 38 - (show annotations)
Mon Oct 8 16:21:53 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 14400 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1515 2007/04/14 05:39:46 debug Exp $
20070324	Adding a "--debug" option to the configure script, to disable
		optimizations in unstable development builds.
		Moving out SCSI-specific stuff from diskimage.c into a new
		diskimage_scsicmd.c.
		Applying Hĺvard Eidnes' patch for SCSICDROM_READ_DISKINFO and
		SCSICDROM_READ_TRACKINFO. (Not really tested yet.)
		Implementing disk image "overlays" (to allow simple roll-back
		to previous disk state). Adding a 'V' disk flag for this, and
		updating the man page and misc.html.
20070325	Stability fix to cpu_dyntrans.c, when multiple physical pages
		share the same initial table entry. (The ppp == NULL check
		should be physpage_ofs == 0.) Bug found by analysing GXemul
		against a version patched for Godson.
		Fixing a second occurance of the same problem (also in
		cpu_dyntrans.c).
		Fixing a MAJOR physical page leak in cpu_dyntrans.c; pages
		weren't _added_ to the set of translated pages, they _replaced_
		all previous pages. It's amazing that this bug has been able
		to live for this long. (Triggered when emulating >128MB RAM.)
20070326	Removing the GDB debugging stub support; it was too hackish
		and ugly.
20070328	Moving around some native code generation skeleton code.
20070329	The -lm check in the configure script now also checks for sin()
		in addition to sqrt(). (Thanks to Nigel Horne for noticing that
		sqrt was not enough on Fedora Core 6.) (Not verified yet.)
20070330	Fixing an indexing bug in dev_sh4.c, found by using gcc version
		4.3.0 20070323.
20070331	Some more experimentation with native code generation.
20070404	Attempting to fix some more SH4 SCIF interrupt bugs; rewriting
		the SH interrupt assertion/deassertion code somewhat.
20070410	Splitting src/file.c into separate files in src/file/.
		Cleanup: Removing the dummy TS7200, Walnut, PB1000, and
		Meshcube emulation modes, and dev_epcom and dev_au1x00.
		Removing the experimental CHIP8/RCA180x code; it wasn't really
		working much lately, anyway. It was fun while it lasted.
		Also removing the experimental Transputer CPU support.
20070412	Moving the section about how the dynamic translation system
		works from intro.html to a separate translation.html file.
		Minor SH fixes; attempting to get OpenBSD/landisk to run
		without randomly bugging out, but no success yet.
20070413	SH SCI (serial bit interface) should now work together with a
		(new) RS5C313 clock device (for Landisk emulation).
20070414	Moving Redhat/MIPS down from supported to experimental, in
		guestoses.html.
		Preparing for a new release; doing some regression testing etc.

==============  RELEASE 0.4.5  ==============


1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_avr.c,v 1.23 2007/03/26 02:01:35 debug Exp $
29 *
30 * Atmel AVR (8-bit) CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "settings.h"
43 #include "symbol.h"
44
45
46 #define DYNTRANS_32
47 #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
48 #include "tmp_avr_head.c"
49
50
51 /*
52 * avr_cpu_new():
53 *
54 * Create a new AVR cpu object.
55 *
56 * Returns 1 on success, 0 if there was no matching AVR processor with
57 * this cpu_type_name.
58 */
59 int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
60 int cpu_id, char *cpu_type_name)
61 {
62 int type = 0, i;
63
64 if (strcasecmp(cpu_type_name, "AVR") == 0 ||
65 strcasecmp(cpu_type_name, "AVR16") == 0 ||
66 strcasecmp(cpu_type_name, "AT90S2313") == 0 ||
67 strcasecmp(cpu_type_name, "AT90S8515") == 0)
68 type = 16;
69 if (strcasecmp(cpu_type_name, "AVR22") == 0)
70 type = 22;
71
72 if (type == 0)
73 return 0;
74
75 cpu->run_instr = avr_run_instr;
76 cpu->memory_rw = avr_memory_rw;
77 cpu->update_translation_table = avr_update_translation_table;
78 cpu->invalidate_translation_caches =
79 avr_invalidate_translation_caches;
80 cpu->invalidate_code_translation = avr_invalidate_code_translation;
81 cpu->is_32bit = 1;
82
83 cpu->byte_order = EMUL_LITTLE_ENDIAN;
84
85 cpu->cd.avr.is_22bit = (type == 22);
86 cpu->cd.avr.pc_mask = cpu->cd.avr.is_22bit? 0x3fffff : 0xffff;
87
88 cpu->cd.avr.sram_mask = 0xff; /* 256 bytes ram */
89 cpu->cd.avr.sp = cpu->cd.avr.sram_mask - 2;
90
91 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
92 if (cpu_id == 0) {
93 debug("%s", cpu->name);
94 }
95
96 CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
97 CPU_SETTINGS_ADD_REGISTER16("sp", cpu->cd.avr.sp);
98 CPU_SETTINGS_ADD_REGISTER8("sreg", cpu->cd.avr.sreg);
99 for (i=0; i<N_AVR_REGS; i++) {
100 char tmpstr[5];
101 snprintf(tmpstr, sizeof(tmpstr), "r%i", i);
102 CPU_SETTINGS_ADD_REGISTER8(tmpstr, cpu->cd.avr.r[i]);
103 }
104
105 return 1;
106 }
107
108
109 /*
110 * avr_cpu_list_available_types():
111 *
112 * Print a list of available AVR CPU types.
113 */
114 void avr_cpu_list_available_types(void)
115 {
116 debug("AVR\tAVR16\tAVR22\n");
117 }
118
119
120 /*
121 * avr_cpu_dumpinfo():
122 */
123 void avr_cpu_dumpinfo(struct cpu *cpu)
124 {
125 debug(" (%i-bit program counter)\n",
126 cpu->cd.avr.is_22bit? 22 : 16);
127 }
128
129
130 /*
131 * avr_cpu_register_dump():
132 *
133 * Dump cpu registers in a relatively readable format.
134 *
135 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
136 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
137 */
138 void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
139 {
140 char *symbol;
141 uint64_t offset;
142 int i, x = cpu->cpu_id;
143
144 if (gprs) {
145 /* Special registers (pc, ...) first: */
146 symbol = get_symbol_name(&cpu->machine->symbol_context,
147 cpu->pc, &offset);
148
149 debug("cpu%i: sreg = ", x);
150 debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i');
151 debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't');
152 debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h');
153 debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's');
154 debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v');
155 debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n');
156 debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z');
157 debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c');
158 if (cpu->cd.avr.is_22bit)
159 debug(" pc = 0x%06x", (int)cpu->pc);
160 else
161 debug(" pc = 0x%04x", (int)cpu->pc);
162 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
163
164 for (i=0; i<N_AVR_REGS; i++) {
165 int r = (i >> 3) + ((i & 7) << 2);
166 if ((i % 8) == 0)
167 debug("cpu%i:", x);
168 debug(" r%-2i=0x%02x", r, cpu->cd.avr.r[r]);
169 if ((i % 8) == 7)
170 debug("\n");
171 }
172
173 debug("cpu%i: x=%i, y=%i, z=%i, sp=0x%04x\n", x,
174 (int)(int16_t)(cpu->cd.avr.r[27]*256 + cpu->cd.avr.r[26]),
175 (int)(int16_t)(cpu->cd.avr.r[29]*256 + cpu->cd.avr.r[28]),
176 (int)(int16_t)(cpu->cd.avr.r[31]*256 + cpu->cd.avr.r[30]),
177 cpu->cd.avr.sp);
178 }
179
180 debug("cpu%i: nr of instructions: %lli\n", x,
181 (long long)cpu->machine->ninstrs);
182 debug("cpu%i: nr of cycles: %lli\n", x,
183 (long long)(cpu->machine->ninstrs + cpu->cd.avr.extra_cycles));
184 }
185
186
187 /*
188 * avr_cpu_tlbdump():
189 *
190 * Called from the debugger to dump the TLB in a readable format.
191 * x is the cpu number to dump, or -1 to dump all CPUs.
192 *
193 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
194 * just dumped.
195 */
196 void avr_cpu_tlbdump(struct machine *m, int x, int rawflag)
197 {
198 }
199
200
201 /* Helper functions: */
202 static void print_two(unsigned char *instr, int *len)
203 { debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; }
204 static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6;
205 i++) debug(" "); }
206
207
208 /*
209 * avr_cpu_disassemble_instr():
210 *
211 * Convert an instruction word into human readable format, for instruction
212 * tracing and disassembly.
213 *
214 * If running is 1, cpu->pc should be the address of the instruction.
215 *
216 * If running is 0, things that depend on the runtime environment (eg.
217 * register contents) will not be shown, and addr will be used instead of
218 * cpu->pc for relative addresses.
219 */
220 int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
221 int running, uint64_t dumpaddr)
222 {
223 uint64_t offset;
224 int len = 0, addr, iw, rd, rr, imm;
225 char *symbol;
226 char *sreg_names = SREG_NAMES;
227
228 if (running)
229 dumpaddr = cpu->pc;
230
231 symbol = get_symbol_name(&cpu->machine->symbol_context,
232 dumpaddr, &offset);
233 if (symbol != NULL && offset==0)
234 debug("<%s>\n", symbol);
235
236 if (cpu->machine->ncpus > 1 && running)
237 debug("cpu%i: ", cpu->cpu_id);
238
239 /* TODO: 22-bit PC */
240 debug("0x%04x: ", (int)dumpaddr);
241
242 print_two(ib, &len);
243 iw = (ib[1] << 8) + ib[0];
244
245 if ((iw & 0xffff) == 0x0000) {
246 print_spaces(len);
247 debug("nop\n");
248 } else if ((iw & 0xff00) == 0x0100) {
249 print_spaces(len);
250 rd = (iw >> 3) & 30;
251 rr = (iw << 1) & 30;
252 debug("movw\tr%i:r%i,r%i:r%i\n", rd+1, rd, rr+1, rr);
253 } else if ((iw & 0xff00) == 0x0200) {
254 print_spaces(len);
255 rd = ((iw >> 4) & 15) + 16;
256 rr = (iw & 15) + 16;
257 debug("muls\tr%i,r%i\n", rd, rr);
258 } else if ((iw & 0xff88) == 0x0300) {
259 print_spaces(len);
260 rd = ((iw >> 4) & 7) + 16;
261 rr = (iw & 7) + 16;
262 debug("mulsu\tr%i,r%i\n", rd, rr);
263 } else if ((iw & 0xff88) == 0x0308) {
264 print_spaces(len);
265 rd = ((iw >> 4) & 7) + 16;
266 rr = (iw & 7) + 16;
267 debug("fmul\tr%i,r%i\n", rd, rr);
268 } else if ((iw & 0xff88) == 0x0380) {
269 print_spaces(len);
270 rd = ((iw >> 4) & 7) + 16;
271 rr = (iw & 7) + 16;
272 debug("fmuls\tr%i,r%i\n", rd, rr);
273 } else if ((iw & 0xff88) == 0x0388) {
274 print_spaces(len);
275 rd = ((iw >> 4) & 7) + 16;
276 rr = (iw & 7) + 16;
277 debug("fmulsu\tr%i,r%i\n", rd, rr);
278 } else if ((iw & 0xec00) == 0x0400) {
279 print_spaces(len);
280 rd = (iw & 0x1f0) >> 4;
281 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
282 debug("cp%s\tr%i,r%i\n", iw & 0x1000? "" : "c", rd, rr);
283 } else if ((iw & 0xec00) == 0x0800) {
284 print_spaces(len);
285 rd = (iw & 0x1f0) >> 4;
286 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
287 debug("%s\tr%i,r%i\n", iw & 0x1000? "sub" : "sbc", rd, rr);
288 } else if ((iw & 0xec00) == 0x0c00) {
289 print_spaces(len);
290 rd = (iw & 0x1f0) >> 4;
291 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
292 debug("%s\tr%i,r%i\n", iw & 0x1000? "adc" : "add", rd, rr);
293 } else if ((iw & 0xfc00) == 0x1000) {
294 print_spaces(len);
295 rd = (iw & 0x1f0) >> 4;
296 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
297 debug("cpse\tr%i,r%i\n", rd, rr);
298 } else if ((iw & 0xfc00) == 0x2000) {
299 print_spaces(len);
300 rd = (iw & 0x1f0) >> 4;
301 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
302 debug("and\tr%i,r%i\n", rd, rr);
303 } else if ((iw & 0xfc00) == 0x2400) {
304 print_spaces(len);
305 rd = (iw & 0x1f0) >> 4;
306 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
307 debug("eor\tr%i,r%i\n", rd, rr);
308 } else if ((iw & 0xfc00) == 0x2800) {
309 print_spaces(len);
310 rd = (iw & 0x1f0) >> 4;
311 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
312 debug("or\tr%i,r%i\n", rd, rr);
313 } else if ((iw & 0xfc00) == 0x2c00) {
314 print_spaces(len);
315 rd = (iw & 0x1f0) >> 4;
316 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
317 debug("mov\tr%i,r%i\n", rd, rr);
318 } else if ((iw & 0xf000) == 0x3000) {
319 print_spaces(len);
320 rd = ((iw >> 4) & 15) + 16;
321 imm = ((iw >> 4) & 0xf0) + (iw & 15);
322 debug("cpi\tr%i,0x%x\n", rd, imm);
323 } else if ((iw & 0xf000) == 0x4000) {
324 print_spaces(len);
325 rd = ((iw >> 4) & 15) + 16;
326 imm = ((iw >> 4) & 0xf0) + (iw & 15);
327 debug("sbci\tr%i,0x%x\n", rd, imm);
328 } else if ((iw & 0xf000) == 0x5000) {
329 print_spaces(len);
330 rd = ((iw >> 4) & 15) + 16;
331 imm = ((iw >> 4) & 0xf0) + (iw & 15);
332 debug("subi\tr%i,0x%x\n", rd, imm);
333 } else if ((iw & 0xe000) == 0x6000) {
334 print_spaces(len);
335 rd = ((iw >> 4) & 15) + 16;
336 imm = ((iw >> 4) & 0xf0) + (iw & 15);
337 debug("%s\tr%i,0x%x\n", iw & 0x1000? "andi" : "ori", rd, imm);
338 } else if ((iw & 0xfe0f) == 0x8000) {
339 print_spaces(len);
340 rd = (iw >> 4) & 31;
341 debug("ld\tr%i,Z\n", rd);
342 } else if ((iw & 0xfe0f) == 0x8008) {
343 print_spaces(len);
344 rd = (iw >> 4) & 31;
345 debug("ld\tr%i,Y\n", rd);
346 } else if ((iw & 0xfe0f) == 0x8208) {
347 print_spaces(len);
348 rd = (iw >> 4) & 31;
349 debug("st\tY,r%i\n", rd);
350 } else if ((iw & 0xfe0f) == 0x900c) {
351 print_spaces(len);
352 rd = (iw >> 4) & 31;
353 debug("ld\tr%i,X\n", rd);
354 } else if ((iw & 0xfc0f) == 0x900f) {
355 print_spaces(len);
356 rd = (iw >> 4) & 31;
357 debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd);
358 } else if ((iw & 0xfe0f) == 0x9000) {
359 print_two(ib, &len);
360 addr = (ib[3] << 8) + ib[2];
361 print_spaces(len);
362 if (iw & 0x200)
363 debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4);
364 else
365 debug("lds\tr%i,0x%x\n", (iw & 0x1f0) >> 4, addr);
366 } else if ((iw & 0xfe0f) == 0x9209) {
367 print_spaces(len);
368 rr = (iw >> 4) & 31;
369 debug("st\tY+,r%i\n", rr);
370 } else if ((iw & 0xfe0f) == 0x920a) {
371 print_spaces(len);
372 rr = (iw >> 4) & 31;
373 debug("st\t-Y,r%i\n", rr);
374 } else if ((iw & 0xfe0f) == 0x9401) {
375 print_spaces(len);
376 rd = (iw >> 4) & 31;
377 debug("neg\tr%i\n", rd);
378 } else if ((iw & 0xfe0f) == 0x9402) {
379 print_spaces(len);
380 rd = (iw >> 4) & 31;
381 debug("swap\tr%i\n", rd);
382 } else if ((iw & 0xfe0f) == 0x9403) {
383 print_spaces(len);
384 rd = (iw >> 4) & 31;
385 debug("inc\tr%i\n", rd);
386 } else if ((iw & 0xff0f) == 0x9408) {
387 print_spaces(len);
388 rd = (iw >> 4) & 7;
389 debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]);
390 } else if ((iw & 0xfe0f) == 0x940a) {
391 print_spaces(len);
392 rd = (iw >> 4) & 31;
393 debug("dec\tr%i\n", rd);
394 } else if ((iw & 0xff8f) == 0x9408) {
395 print_spaces(len);
396 debug("bset\t%i\n", (iw >> 4) & 7);
397 } else if ((iw & 0xff8f) == 0x9488) {
398 print_spaces(len);
399 debug("bclr\t%i\n", (iw >> 4) & 7);
400 } else if ((iw & 0xffef) == 0x9508) {
401 /* ret and reti */
402 print_spaces(len);
403 debug("ret%s\n", (iw & 0x10)? "i" : "");
404 } else if ((iw & 0xffff) == 0x9588) {
405 print_spaces(len);
406 debug("sleep\n");
407 } else if ((iw & 0xffff) == 0x9598) {
408 print_spaces(len);
409 debug("break\n");
410 } else if ((iw & 0xffff) == 0x95a8) {
411 print_spaces(len);
412 debug("wdr\n");
413 } else if ((iw & 0xffef) == 0x95c8) {
414 print_spaces(len);
415 debug("%slpm\n", iw & 0x0010? "e" : "");
416 } else if ((iw & 0xff00) == 0x9600) {
417 print_spaces(len);
418 imm = ((iw & 0xc0) >> 2) | (iw & 0xf);
419 rd = ((iw >> 4) & 3) * 2 + 24;
420 debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm);
421 } else if ((iw & 0xfd00) == 0x9800) {
422 print_spaces(len);
423 imm = iw & 7;
424 rd = (iw >> 3) & 31; /* A */
425 debug("%sbi\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm);
426 } else if ((iw & 0xfd00) == 0x9900) {
427 print_spaces(len);
428 imm = iw & 7;
429 rd = (iw >> 3) & 31; /* A */
430 debug("sbi%s\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm);
431 } else if ((iw & 0xf000) == 0xb000) {
432 print_spaces(len);
433 imm = ((iw & 0x600) >> 5) | (iw & 0xf);
434 rr = (iw >> 4) & 31;
435 if (iw & 0x800)
436 debug("out\t0x%x,r%i\n", imm, rr);
437 else
438 debug("in\tr%i,0x%x\n", rr, imm);
439 } else if ((iw & 0xe000) == 0xc000) {
440 print_spaces(len);
441 addr = (int16_t)((iw & 0xfff) << 4);
442 addr = (addr >> 3) + dumpaddr + 2;
443 debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr);
444 } else if ((iw & 0xf000) == 0xe000) {
445 print_spaces(len);
446 rd = ((iw >> 4) & 0xf) + 16;
447 imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
448 debug("ldi\tr%i,0x%x\n", rd, imm);
449 } else if ((iw & 0xfc00) == 0xf000) {
450 print_spaces(len);
451 addr = (iw >> 3) & 0x7f;
452 if (addr >= 64)
453 addr -= 128;
454 addr = (addr + 1) * 2 + dumpaddr;
455 debug("brbs\t%c,0x%x\n", sreg_names[iw & 7], addr);
456 } else if ((iw & 0xfc00) == 0xf400) {
457 print_spaces(len);
458 addr = (iw >> 3) & 0x7f;
459 if (addr >= 64)
460 addr -= 128;
461 addr = (addr + 1) * 2 + dumpaddr;
462 debug("brbc\t%c,0x%x\n", sreg_names[iw & 7], addr);
463 } else if ((iw & 0xfc08) == 0xfc00) {
464 print_spaces(len);
465 rr = (iw >> 4) & 31;
466 imm = iw & 7;
467 debug("sbr%s\tr%i,%i\n", iw & 0x0200 ? "s" : "c", rr, imm);
468 } else {
469 print_spaces(len);
470 debug("UNIMPLEMENTED 0x%04x\n", iw);
471 }
472
473 return len;
474 }
475
476
477 #include "tmp_avr_tail.c"
478

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