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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_avr.c,v 1.23 2007/03/26 02:01:35 debug Exp $ |
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* |
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* Atmel AVR (8-bit) CPU emulation. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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|
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
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|
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|
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#define DYNTRANS_32 |
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#define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
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#include "tmp_avr_head.c" |
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|
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|
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/* |
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* avr_cpu_new(): |
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* |
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* Create a new AVR cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching AVR processor with |
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* this cpu_type_name. |
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*/ |
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int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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int type = 0, i; |
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|
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if (strcasecmp(cpu_type_name, "AVR") == 0 || |
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strcasecmp(cpu_type_name, "AVR16") == 0 || |
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strcasecmp(cpu_type_name, "AT90S2313") == 0 || |
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strcasecmp(cpu_type_name, "AT90S8515") == 0) |
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type = 16; |
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if (strcasecmp(cpu_type_name, "AVR22") == 0) |
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type = 22; |
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|
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if (type == 0) |
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return 0; |
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|
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cpu->run_instr = avr_run_instr; |
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cpu->memory_rw = avr_memory_rw; |
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cpu->update_translation_table = avr_update_translation_table; |
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cpu->invalidate_translation_caches = |
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avr_invalidate_translation_caches; |
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cpu->invalidate_code_translation = avr_invalidate_code_translation; |
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cpu->is_32bit = 1; |
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|
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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|
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cpu->cd.avr.is_22bit = (type == 22); |
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cpu->cd.avr.pc_mask = cpu->cd.avr.is_22bit? 0x3fffff : 0xffff; |
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|
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cpu->cd.avr.sram_mask = 0xff; /* 256 bytes ram */ |
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cpu->cd.avr.sp = cpu->cd.avr.sram_mask - 2; |
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|
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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|
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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CPU_SETTINGS_ADD_REGISTER16("sp", cpu->cd.avr.sp); |
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CPU_SETTINGS_ADD_REGISTER8("sreg", cpu->cd.avr.sreg); |
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for (i=0; i<N_AVR_REGS; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
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CPU_SETTINGS_ADD_REGISTER8(tmpstr, cpu->cd.avr.r[i]); |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* avr_cpu_list_available_types(): |
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* |
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* Print a list of available AVR CPU types. |
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*/ |
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void avr_cpu_list_available_types(void) |
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{ |
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debug("AVR\tAVR16\tAVR22\n"); |
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} |
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|
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|
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/* |
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* avr_cpu_dumpinfo(): |
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*/ |
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void avr_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug(" (%i-bit program counter)\n", |
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cpu->cd.avr.is_22bit? 22 : 16); |
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} |
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|
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|
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/* |
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* avr_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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|
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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|
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debug("cpu%i: sreg = ", x); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c'); |
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if (cpu->cd.avr.is_22bit) |
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debug(" pc = 0x%06x", (int)cpu->pc); |
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else |
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debug(" pc = 0x%04x", (int)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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|
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for (i=0; i<N_AVR_REGS; i++) { |
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int r = (i >> 3) + ((i & 7) << 2); |
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if ((i % 8) == 0) |
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debug("cpu%i:", x); |
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debug(" r%-2i=0x%02x", r, cpu->cd.avr.r[r]); |
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if ((i % 8) == 7) |
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debug("\n"); |
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} |
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|
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debug("cpu%i: x=%i, y=%i, z=%i, sp=0x%04x\n", x, |
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(int)(int16_t)(cpu->cd.avr.r[27]*256 + cpu->cd.avr.r[26]), |
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(int)(int16_t)(cpu->cd.avr.r[29]*256 + cpu->cd.avr.r[28]), |
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(int)(int16_t)(cpu->cd.avr.r[31]*256 + cpu->cd.avr.r[30]), |
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cpu->cd.avr.sp); |
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} |
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|
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debug("cpu%i: nr of instructions: %lli\n", x, |
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(long long)cpu->machine->ninstrs); |
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debug("cpu%i: nr of cycles: %lli\n", x, |
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(long long)(cpu->machine->ninstrs + cpu->cd.avr.extra_cycles)); |
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} |
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|
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|
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/* |
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* avr_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void avr_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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|
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|
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/* Helper functions: */ |
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static void print_two(unsigned char *instr, int *len) |
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{ debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; } |
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static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6; |
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i++) debug(" "); } |
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|
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|
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/* |
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* avr_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing and disassembly. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr) |
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{ |
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uint64_t offset; |
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int len = 0, addr, iw, rd, rr, imm; |
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char *symbol; |
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char *sreg_names = SREG_NAMES; |
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|
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if (running) |
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dumpaddr = cpu->pc; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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|
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
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|
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/* TODO: 22-bit PC */ |
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debug("0x%04x: ", (int)dumpaddr); |
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|
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print_two(ib, &len); |
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iw = (ib[1] << 8) + ib[0]; |
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|
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if ((iw & 0xffff) == 0x0000) { |
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print_spaces(len); |
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debug("nop\n"); |
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} else if ((iw & 0xff00) == 0x0100) { |
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print_spaces(len); |
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rd = (iw >> 3) & 30; |
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rr = (iw << 1) & 30; |
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debug("movw\tr%i:r%i,r%i:r%i\n", rd+1, rd, rr+1, rr); |
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} else if ((iw & 0xff00) == 0x0200) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 15) + 16; |
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rr = (iw & 15) + 16; |
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debug("muls\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xff88) == 0x0300) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 7) + 16; |
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rr = (iw & 7) + 16; |
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debug("mulsu\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xff88) == 0x0308) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 7) + 16; |
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rr = (iw & 7) + 16; |
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debug("fmul\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xff88) == 0x0380) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 7) + 16; |
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rr = (iw & 7) + 16; |
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debug("fmuls\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xff88) == 0x0388) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 7) + 16; |
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rr = (iw & 7) + 16; |
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debug("fmulsu\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xec00) == 0x0400) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("cp%s\tr%i,r%i\n", iw & 0x1000? "" : "c", rd, rr); |
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} else if ((iw & 0xec00) == 0x0800) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("%s\tr%i,r%i\n", iw & 0x1000? "sub" : "sbc", rd, rr); |
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} else if ((iw & 0xec00) == 0x0c00) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("%s\tr%i,r%i\n", iw & 0x1000? "adc" : "add", rd, rr); |
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} else if ((iw & 0xfc00) == 0x1000) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("cpse\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2000) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("and\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2400) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("eor\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2800) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("or\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xfc00) == 0x2c00) { |
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print_spaces(len); |
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rd = (iw & 0x1f0) >> 4; |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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debug("mov\tr%i,r%i\n", rd, rr); |
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} else if ((iw & 0xf000) == 0x3000) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 15) + 16; |
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imm = ((iw >> 4) & 0xf0) + (iw & 15); |
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debug("cpi\tr%i,0x%x\n", rd, imm); |
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} else if ((iw & 0xf000) == 0x4000) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 15) + 16; |
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imm = ((iw >> 4) & 0xf0) + (iw & 15); |
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debug("sbci\tr%i,0x%x\n", rd, imm); |
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} else if ((iw & 0xf000) == 0x5000) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 15) + 16; |
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imm = ((iw >> 4) & 0xf0) + (iw & 15); |
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debug("subi\tr%i,0x%x\n", rd, imm); |
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} else if ((iw & 0xe000) == 0x6000) { |
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print_spaces(len); |
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rd = ((iw >> 4) & 15) + 16; |
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imm = ((iw >> 4) & 0xf0) + (iw & 15); |
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debug("%s\tr%i,0x%x\n", iw & 0x1000? "andi" : "ori", rd, imm); |
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} else if ((iw & 0xfe0f) == 0x8000) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
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debug("ld\tr%i,Z\n", rd); |
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} else if ((iw & 0xfe0f) == 0x8008) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
345 |
debug("ld\tr%i,Y\n", rd); |
346 |
} else if ((iw & 0xfe0f) == 0x8208) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
349 |
debug("st\tY,r%i\n", rd); |
350 |
} else if ((iw & 0xfe0f) == 0x900c) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
353 |
debug("ld\tr%i,X\n", rd); |
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} else if ((iw & 0xfc0f) == 0x900f) { |
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print_spaces(len); |
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rd = (iw >> 4) & 31; |
357 |
debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd); |
358 |
} else if ((iw & 0xfe0f) == 0x9000) { |
359 |
print_two(ib, &len); |
360 |
addr = (ib[3] << 8) + ib[2]; |
361 |
print_spaces(len); |
362 |
if (iw & 0x200) |
363 |
debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4); |
364 |
else |
365 |
debug("lds\tr%i,0x%x\n", (iw & 0x1f0) >> 4, addr); |
366 |
} else if ((iw & 0xfe0f) == 0x9209) { |
367 |
print_spaces(len); |
368 |
rr = (iw >> 4) & 31; |
369 |
debug("st\tY+,r%i\n", rr); |
370 |
} else if ((iw & 0xfe0f) == 0x920a) { |
371 |
print_spaces(len); |
372 |
rr = (iw >> 4) & 31; |
373 |
debug("st\t-Y,r%i\n", rr); |
374 |
} else if ((iw & 0xfe0f) == 0x9401) { |
375 |
print_spaces(len); |
376 |
rd = (iw >> 4) & 31; |
377 |
debug("neg\tr%i\n", rd); |
378 |
} else if ((iw & 0xfe0f) == 0x9402) { |
379 |
print_spaces(len); |
380 |
rd = (iw >> 4) & 31; |
381 |
debug("swap\tr%i\n", rd); |
382 |
} else if ((iw & 0xfe0f) == 0x9403) { |
383 |
print_spaces(len); |
384 |
rd = (iw >> 4) & 31; |
385 |
debug("inc\tr%i\n", rd); |
386 |
} else if ((iw & 0xff0f) == 0x9408) { |
387 |
print_spaces(len); |
388 |
rd = (iw >> 4) & 7; |
389 |
debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]); |
390 |
} else if ((iw & 0xfe0f) == 0x940a) { |
391 |
print_spaces(len); |
392 |
rd = (iw >> 4) & 31; |
393 |
debug("dec\tr%i\n", rd); |
394 |
} else if ((iw & 0xff8f) == 0x9408) { |
395 |
print_spaces(len); |
396 |
debug("bset\t%i\n", (iw >> 4) & 7); |
397 |
} else if ((iw & 0xff8f) == 0x9488) { |
398 |
print_spaces(len); |
399 |
debug("bclr\t%i\n", (iw >> 4) & 7); |
400 |
} else if ((iw & 0xffef) == 0x9508) { |
401 |
/* ret and reti */ |
402 |
print_spaces(len); |
403 |
debug("ret%s\n", (iw & 0x10)? "i" : ""); |
404 |
} else if ((iw & 0xffff) == 0x9588) { |
405 |
print_spaces(len); |
406 |
debug("sleep\n"); |
407 |
} else if ((iw & 0xffff) == 0x9598) { |
408 |
print_spaces(len); |
409 |
debug("break\n"); |
410 |
} else if ((iw & 0xffff) == 0x95a8) { |
411 |
print_spaces(len); |
412 |
debug("wdr\n"); |
413 |
} else if ((iw & 0xffef) == 0x95c8) { |
414 |
print_spaces(len); |
415 |
debug("%slpm\n", iw & 0x0010? "e" : ""); |
416 |
} else if ((iw & 0xff00) == 0x9600) { |
417 |
print_spaces(len); |
418 |
imm = ((iw & 0xc0) >> 2) | (iw & 0xf); |
419 |
rd = ((iw >> 4) & 3) * 2 + 24; |
420 |
debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm); |
421 |
} else if ((iw & 0xfd00) == 0x9800) { |
422 |
print_spaces(len); |
423 |
imm = iw & 7; |
424 |
rd = (iw >> 3) & 31; /* A */ |
425 |
debug("%sbi\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm); |
426 |
} else if ((iw & 0xfd00) == 0x9900) { |
427 |
print_spaces(len); |
428 |
imm = iw & 7; |
429 |
rd = (iw >> 3) & 31; /* A */ |
430 |
debug("sbi%s\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm); |
431 |
} else if ((iw & 0xf000) == 0xb000) { |
432 |
print_spaces(len); |
433 |
imm = ((iw & 0x600) >> 5) | (iw & 0xf); |
434 |
rr = (iw >> 4) & 31; |
435 |
if (iw & 0x800) |
436 |
debug("out\t0x%x,r%i\n", imm, rr); |
437 |
else |
438 |
debug("in\tr%i,0x%x\n", rr, imm); |
439 |
} else if ((iw & 0xe000) == 0xc000) { |
440 |
print_spaces(len); |
441 |
addr = (int16_t)((iw & 0xfff) << 4); |
442 |
addr = (addr >> 3) + dumpaddr + 2; |
443 |
debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr); |
444 |
} else if ((iw & 0xf000) == 0xe000) { |
445 |
print_spaces(len); |
446 |
rd = ((iw >> 4) & 0xf) + 16; |
447 |
imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
448 |
debug("ldi\tr%i,0x%x\n", rd, imm); |
449 |
} else if ((iw & 0xfc00) == 0xf000) { |
450 |
print_spaces(len); |
451 |
addr = (iw >> 3) & 0x7f; |
452 |
if (addr >= 64) |
453 |
addr -= 128; |
454 |
addr = (addr + 1) * 2 + dumpaddr; |
455 |
debug("brbs\t%c,0x%x\n", sreg_names[iw & 7], addr); |
456 |
} else if ((iw & 0xfc00) == 0xf400) { |
457 |
print_spaces(len); |
458 |
addr = (iw >> 3) & 0x7f; |
459 |
if (addr >= 64) |
460 |
addr -= 128; |
461 |
addr = (addr + 1) * 2 + dumpaddr; |
462 |
debug("brbc\t%c,0x%x\n", sreg_names[iw & 7], addr); |
463 |
} else if ((iw & 0xfc08) == 0xfc00) { |
464 |
print_spaces(len); |
465 |
rr = (iw >> 4) & 31; |
466 |
imm = iw & 7; |
467 |
debug("sbr%s\tr%i,%i\n", iw & 0x0200 ? "s" : "c", rr, imm); |
468 |
} else { |
469 |
print_spaces(len); |
470 |
debug("UNIMPLEMENTED 0x%04x\n", iw); |
471 |
} |
472 |
|
473 |
return len; |
474 |
} |
475 |
|
476 |
|
477 |
#include "tmp_avr_tail.c" |
478 |
|