/[gxemul]/trunk/src/cpus/cpu_avr.c
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Contents of /trunk/src/cpus/cpu_avr.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (12 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 9208 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_avr.c,v 1.7 2005/11/13 00:14:07 debug Exp $
29 *
30 * Atmel AVR (8-bit) CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "symbol.h"
43
44
45 #define DYNTRANS_32
46 #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
47 #include "tmp_avr_head.c"
48
49
50 /*
51 * avr_cpu_new():
52 *
53 * Create a new AVR cpu object.
54 *
55 * Returns 1 on success, 0 if there was no matching AVR processor with
56 * this cpu_type_name.
57 */
58 int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
59 int cpu_id, char *cpu_type_name)
60 {
61 if (strcasecmp(cpu_type_name, "AVR") != 0)
62 return 0;
63
64 cpu->memory_rw = avr_memory_rw;
65 cpu->update_translation_table = avr_update_translation_table;
66 cpu->invalidate_translation_caches =
67 avr_invalidate_translation_caches;
68 cpu->invalidate_code_translation = avr_invalidate_code_translation;
69 cpu->is_32bit = 1;
70
71 cpu->byte_order = EMUL_LITTLE_ENDIAN;
72
73 cpu->cd.avr.pc_mask = 0xffff;
74
75 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
76 if (cpu_id == 0) {
77 debug("%s", cpu->name);
78 }
79
80 return 1;
81 }
82
83
84 /*
85 * avr_cpu_list_available_types():
86 *
87 * Print a list of available AVR CPU types.
88 */
89 void avr_cpu_list_available_types(void)
90 {
91 debug("AVR\n");
92 /* TODO */
93 }
94
95
96 /*
97 * avr_cpu_dumpinfo():
98 */
99 void avr_cpu_dumpinfo(struct cpu *cpu)
100 {
101 /* TODO */
102 debug("\n");
103 }
104
105
106 /*
107 * avr_cpu_register_dump():
108 *
109 * Dump cpu registers in a relatively readable format.
110 *
111 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
112 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
113 */
114 void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
115 {
116 char *symbol;
117 uint64_t offset;
118 int i, x = cpu->cpu_id;
119
120 if (gprs) {
121 /* Special registers (pc, ...) first: */
122 symbol = get_symbol_name(&cpu->machine->symbol_context,
123 cpu->pc, &offset);
124
125 debug("cpu%i: sreg = ", x);
126 debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i');
127 debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't');
128 debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h');
129 debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's');
130 debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v');
131 debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n');
132 debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z');
133 debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c');
134 debug(" pc = 0x%04x", x, (int)cpu->pc);
135 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
136
137 for (i=0; i<N_AVR_REGS; i++) {
138 if ((i % 4) == 0)
139 debug("cpu%i:\t", x);
140 debug("r%02i = 0x%02x", i, cpu->cd.avr.r[i]);
141 debug((i % 4) == 3? "\n" : " ");
142 }
143 }
144
145 debug("cpu%i: nr of instructions: %lli\n", x,
146 (long long)cpu->machine->ncycles);
147 debug("cpu%i: nr of cycles: %lli\n", x,
148 (long long)(cpu->machine->ncycles + cpu->cd.avr.extra_cycles));
149 }
150
151
152 /*
153 * avr_cpu_register_match():
154 */
155 void avr_cpu_register_match(struct machine *m, char *name,
156 int writeflag, uint64_t *valuep, int *match_register)
157 {
158 int cpunr = 0;
159
160 /* CPU number: */
161 /* TODO */
162
163 if (strcasecmp(name, "pc") == 0) {
164 if (writeflag) {
165 m->cpus[cpunr]->pc = *valuep;
166 } else
167 *valuep = m->cpus[cpunr]->pc;
168 *match_register = 1;
169 } else if (name[0] == 'r' && isdigit((int)name[1])) {
170 int nr = atoi(name + 1);
171 if (nr >= 0 && nr < N_AVR_REGS) {
172 if (writeflag)
173 m->cpus[cpunr]->cd.avr.r[nr] = *valuep;
174 else
175 *valuep = m->cpus[cpunr]->cd.avr.r[nr];
176 *match_register = 1;
177 }
178 }
179 }
180
181
182 /*
183 * avr_cpu_interrupt():
184 */
185 int avr_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
186 {
187 fatal("avr_cpu_interrupt(): TODO\n");
188 return 0;
189 }
190
191
192 /*
193 * avr_cpu_interrupt_ack():
194 */
195 int avr_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
196 {
197 /* fatal("avr_cpu_interrupt_ack(): TODO\n"); */
198 return 0;
199 }
200
201
202 /* Helper functions: */
203 static void print_two(unsigned char *instr, int *len)
204 { debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; }
205 static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6;
206 i++) debug(" "); }
207
208
209 /*
210 * avr_cpu_disassemble_instr():
211 *
212 * Convert an instruction word into human readable format, for instruction
213 * tracing and disassembly.
214 *
215 * If running is 1, cpu->pc should be the address of the instruction.
216 *
217 * If running is 0, things that depend on the runtime environment (eg.
218 * register contents) will not be shown, and addr will be used instead of
219 * cpu->pc for relative addresses.
220 */
221 int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
222 int running, uint64_t dumpaddr, int bintrans)
223 {
224 uint64_t offset;
225 int len = 0, addr, iw, rd, rr, imm;
226 char *symbol;
227 char *sreg_names = SREG_NAMES;
228
229 if (running)
230 dumpaddr = cpu->pc;
231
232 symbol = get_symbol_name(&cpu->machine->symbol_context,
233 dumpaddr, &offset);
234 if (symbol != NULL && offset==0)
235 debug("<%s>\n", symbol);
236
237 if (cpu->machine->ncpus > 1 && running)
238 debug("cpu%i: ", cpu->cpu_id);
239
240 /* TODO: 22-bit PC */
241 debug("0x%04x: ", (int)dumpaddr);
242
243 print_two(ib, &len);
244 iw = (ib[1] << 8) + ib[0];
245
246 if ((iw & 0xffff) == 0x0000) {
247 print_spaces(len);
248 debug("nop\n");
249 } else if ((iw & 0xfc00) == 0x0c00) {
250 print_spaces(len);
251 rd = (iw & 0x1f0) >> 4;
252 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
253 debug("add\tr%i,r%i\n", rd, rr);
254 } else if ((iw & 0xfc00) == 0x1c00) {
255 print_spaces(len);
256 rd = (iw & 0x1f0) >> 4;
257 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
258 debug("adc\tr%i,r%i\n", rd, rr);
259 } else if ((iw & 0xfc00) == 0x2000) {
260 print_spaces(len);
261 rd = (iw & 0x1f0) >> 4;
262 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
263 debug("and\tr%i,r%i\n", rd, rr);
264 } else if ((iw & 0xfc00) == 0x2c00) {
265 print_spaces(len);
266 rd = (iw & 0x1f0) >> 4;
267 rr = ((iw & 0x200) >> 5) | (iw & 0xf);
268 debug("mov\tr%i,r%i\n", rd, rr);
269 } else if ((iw & 0xfe0f) == 0x8000) {
270 print_spaces(len);
271 rd = (iw >> 4) & 31;
272 debug("ld\tr%i,Z\n", rd);
273 } else if ((iw & 0xfe0f) == 0x8008) {
274 print_spaces(len);
275 rd = (iw >> 4) & 31;
276 debug("ld\tr%i,Y\n", rd);
277 } else if ((iw & 0xfe0f) == 0x900c) {
278 print_spaces(len);
279 rd = (iw >> 4) & 31;
280 debug("ld\tr%i,X\n", rd);
281 } else if ((iw & 0xfc0f) == 0x900f) {
282 print_spaces(len);
283 rd = (iw >> 4) & 31;
284 debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd);
285 } else if ((iw & 0xfe0f) == 0x9200) {
286 print_two(ib, &len);
287 addr = (ib[3] << 8) + ib[2];
288 print_spaces(len);
289 debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4);
290 } else if ((iw & 0xfe0f) == 0x9402) {
291 print_spaces(len);
292 rd = (iw >> 4) & 31;
293 debug("swap\tr%i\n", rd);
294 } else if ((iw & 0xff0f) == 0x9408) {
295 print_spaces(len);
296 rd = (iw >> 4) & 7;
297 debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]);
298 } else if ((iw & 0xffef) == 0x9508) {
299 /* ret and reti */
300 print_spaces(len);
301 debug("ret%s\n", (iw & 0x10)? "i" : "");
302 } else if ((iw & 0xffff) == 0x9588) {
303 print_spaces(len);
304 debug("sleep\n");
305 } else if ((iw & 0xffff) == 0x95a8) {
306 print_spaces(len);
307 debug("wdr\n");
308 } else if ((iw & 0xff00) == 0x9600) {
309 print_spaces(len);
310 imm = ((iw & 0xc0) >> 2) | (iw & 0xf);
311 rd = ((iw >> 4) & 3) * 2 + 24;
312 debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm);
313 } else if ((iw & 0xe000) == 0xc000) {
314 print_spaces(len);
315 addr = (int16_t)((iw & 0xfff) << 4);
316 addr = (addr >> 3) + dumpaddr + 2;
317 debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr);
318 } else if ((iw & 0xf000) == 0xe000) {
319 print_spaces(len);
320 rd = ((iw >> 4) & 0xf) + 16;
321 imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
322 debug("ldi\tr%i,0x%x\n", rd, imm);
323 } else {
324 print_spaces(len);
325 debug("UNIMPLEMENTED 0x%04x\n", iw);
326 }
327
328 return len;
329 }
330
331
332 #include "tmp_avr_tail.c"
333

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