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dpavlin |
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/* |
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dpavlin |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_avr.c,v 1.20 2006/07/16 13:32:26 debug Exp $ |
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* |
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* Atmel AVR (8-bit) CPU emulation. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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#define DYNTRANS_32 |
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#define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
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#include "tmp_avr_head.c" |
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/* |
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* avr_cpu_new(): |
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* |
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* Create a new AVR cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching AVR processor with |
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* this cpu_type_name. |
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*/ |
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int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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int type = 0; |
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if (strcasecmp(cpu_type_name, "AVR") == 0 || |
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strcasecmp(cpu_type_name, "AVR16") == 0 || |
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strcasecmp(cpu_type_name, "AT90S2313") == 0 || |
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strcasecmp(cpu_type_name, "AT90S8515") == 0) |
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type = 16; |
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if (strcasecmp(cpu_type_name, "AVR22") == 0) |
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type = 22; |
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if (type == 0) |
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return 0; |
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cpu->run_instr = avr_run_instr; |
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cpu->memory_rw = avr_memory_rw; |
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cpu->update_translation_table = avr_update_translation_table; |
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cpu->invalidate_translation_caches = |
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avr_invalidate_translation_caches; |
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cpu->invalidate_code_translation = avr_invalidate_code_translation; |
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cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->cd.avr.is_22bit = (type == 22); |
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cpu->cd.avr.pc_mask = cpu->cd.avr.is_22bit? 0x3fffff : 0xffff; |
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cpu->cd.avr.sram_mask = 0xff; /* 256 bytes ram */ |
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cpu->cd.avr.sp = cpu->cd.avr.sram_mask - 2; |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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return 1; |
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} |
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/* |
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* avr_cpu_list_available_types(): |
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* |
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* Print a list of available AVR CPU types. |
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*/ |
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void avr_cpu_list_available_types(void) |
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{ |
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debug("AVR\tAVR16\tAVR22\n"); |
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} |
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/* |
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* avr_cpu_dumpinfo(): |
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*/ |
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void avr_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug(" (%i-bit program counter)\n", |
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cpu->cd.avr.is_22bit? 22 : 16); |
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} |
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/* |
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* avr_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: sreg = ", x); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z'); |
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debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c'); |
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dpavlin |
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if (cpu->cd.avr.is_22bit) |
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debug(" pc = 0x%06x", (int)cpu->pc); |
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else |
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debug(" pc = 0x%04x", (int)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_AVR_REGS; i++) { |
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int r = (i >> 3) + ((i & 7) << 2); |
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if ((i % 8) == 0) |
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debug("cpu%i:", x); |
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debug(" r%02i=0x%02x", r, cpu->cd.avr.r[r]); |
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if ((i % 8) == 7) |
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debug("\n"); |
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} |
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debug("cpu%i: x=%i, y=%i, z=%i, sp=0x%04x\n", x, |
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(int)(int16_t)(cpu->cd.avr.r[27]*256 + cpu->cd.avr.r[26]), |
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(int)(int16_t)(cpu->cd.avr.r[29]*256 + cpu->cd.avr.r[28]), |
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(int)(int16_t)(cpu->cd.avr.r[31]*256 + cpu->cd.avr.r[30]), |
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cpu->cd.avr.sp); |
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} |
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debug("cpu%i: nr of instructions: %lli\n", x, |
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(long long)cpu->machine->ninstrs); |
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debug("cpu%i: nr of cycles: %lli\n", x, |
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(long long)(cpu->machine->ninstrs + cpu->cd.avr.extra_cycles)); |
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} |
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/* |
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* avr_cpu_register_match(): |
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*/ |
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void avr_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} else if (name[0] == 'r' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < N_AVR_REGS) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.avr.r[nr] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.avr.r[nr]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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* avr_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void avr_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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/* |
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* avr_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *avr_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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fatal("avr_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
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/* |
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dpavlin |
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* avr_cpu_interrupt(): |
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*/ |
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int avr_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("avr_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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/* |
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* avr_cpu_interrupt_ack(): |
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*/ |
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int avr_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("avr_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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/* Helper functions: */ |
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static void print_two(unsigned char *instr, int *len) |
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{ debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; } |
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static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6; |
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i++) debug(" "); } |
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/* |
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* avr_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing and disassembly. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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dpavlin |
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int running, uint64_t dumpaddr) |
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dpavlin |
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{ |
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uint64_t offset; |
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int len = 0, addr, iw, rd, rr, imm; |
| 278 |
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char *symbol; |
| 279 |
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char *sreg_names = SREG_NAMES; |
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if (running) |
| 282 |
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dumpaddr = cpu->pc; |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
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/* TODO: 22-bit PC */ |
| 293 |
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debug("0x%04x: ", (int)dumpaddr); |
| 294 |
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| 295 |
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print_two(ib, &len); |
| 296 |
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iw = (ib[1] << 8) + ib[0]; |
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| 298 |
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if ((iw & 0xffff) == 0x0000) { |
| 299 |
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print_spaces(len); |
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debug("nop\n"); |
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dpavlin |
24 |
} else if ((iw & 0xff00) == 0x0100) { |
| 302 |
dpavlin |
14 |
print_spaces(len); |
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dpavlin |
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rd = (iw >> 3) & 30; |
| 304 |
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rr = (iw << 1) & 30; |
| 305 |
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debug("movw\tr%i:r%i,r%i:r%i\n", rd+1, rd, rr+1, rr); |
| 306 |
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} else if ((iw & 0xff00) == 0x0200) { |
| 307 |
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print_spaces(len); |
| 308 |
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rd = ((iw >> 4) & 15) + 16; |
| 309 |
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rr = (iw & 15) + 16; |
| 310 |
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debug("muls\tr%i,r%i\n", rd, rr); |
| 311 |
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} else if ((iw & 0xff88) == 0x0300) { |
| 312 |
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print_spaces(len); |
| 313 |
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rd = ((iw >> 4) & 7) + 16; |
| 314 |
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rr = (iw & 7) + 16; |
| 315 |
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debug("mulsu\tr%i,r%i\n", rd, rr); |
| 316 |
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} else if ((iw & 0xff88) == 0x0308) { |
| 317 |
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print_spaces(len); |
| 318 |
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rd = ((iw >> 4) & 7) + 16; |
| 319 |
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rr = (iw & 7) + 16; |
| 320 |
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debug("fmul\tr%i,r%i\n", rd, rr); |
| 321 |
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} else if ((iw & 0xff88) == 0x0380) { |
| 322 |
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print_spaces(len); |
| 323 |
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rd = ((iw >> 4) & 7) + 16; |
| 324 |
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rr = (iw & 7) + 16; |
| 325 |
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debug("fmuls\tr%i,r%i\n", rd, rr); |
| 326 |
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} else if ((iw & 0xff88) == 0x0388) { |
| 327 |
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print_spaces(len); |
| 328 |
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rd = ((iw >> 4) & 7) + 16; |
| 329 |
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rr = (iw & 7) + 16; |
| 330 |
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debug("fmulsu\tr%i,r%i\n", rd, rr); |
| 331 |
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} else if ((iw & 0xec00) == 0x0400) { |
| 332 |
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print_spaces(len); |
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dpavlin |
14 |
rd = (iw & 0x1f0) >> 4; |
| 334 |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
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dpavlin |
24 |
debug("cp%s\tr%i,r%i\n", iw & 0x1000? "" : "c", rd, rr); |
| 336 |
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} else if ((iw & 0xec00) == 0x0800) { |
| 337 |
dpavlin |
14 |
print_spaces(len); |
| 338 |
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rd = (iw & 0x1f0) >> 4; |
| 339 |
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rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 340 |
dpavlin |
24 |
debug("%s\tr%i,r%i\n", iw & 0x1000? "sub" : "sbc", rd, rr); |
| 341 |
|
|
} else if ((iw & 0xec00) == 0x0c00) { |
| 342 |
|
|
print_spaces(len); |
| 343 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 344 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 345 |
|
|
debug("%s\tr%i,r%i\n", iw & 0x1000? "adc" : "add", rd, rr); |
| 346 |
|
|
} else if ((iw & 0xfc00) == 0x1000) { |
| 347 |
|
|
print_spaces(len); |
| 348 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 349 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 350 |
|
|
debug("cpse\tr%i,r%i\n", rd, rr); |
| 351 |
dpavlin |
14 |
} else if ((iw & 0xfc00) == 0x2000) { |
| 352 |
|
|
print_spaces(len); |
| 353 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 354 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 355 |
|
|
debug("and\tr%i,r%i\n", rd, rr); |
| 356 |
dpavlin |
24 |
} else if ((iw & 0xfc00) == 0x2400) { |
| 357 |
|
|
print_spaces(len); |
| 358 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 359 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 360 |
|
|
debug("eor\tr%i,r%i\n", rd, rr); |
| 361 |
|
|
} else if ((iw & 0xfc00) == 0x2800) { |
| 362 |
|
|
print_spaces(len); |
| 363 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 364 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 365 |
|
|
debug("or\tr%i,r%i\n", rd, rr); |
| 366 |
dpavlin |
14 |
} else if ((iw & 0xfc00) == 0x2c00) { |
| 367 |
|
|
print_spaces(len); |
| 368 |
|
|
rd = (iw & 0x1f0) >> 4; |
| 369 |
|
|
rr = ((iw & 0x200) >> 5) | (iw & 0xf); |
| 370 |
|
|
debug("mov\tr%i,r%i\n", rd, rr); |
| 371 |
dpavlin |
24 |
} else if ((iw & 0xf000) == 0x3000) { |
| 372 |
|
|
print_spaces(len); |
| 373 |
|
|
rd = ((iw >> 4) & 15) + 16; |
| 374 |
|
|
imm = ((iw >> 4) & 0xf0) + (iw & 15); |
| 375 |
|
|
debug("cpi\tr%i,0x%x\n", rd, imm); |
| 376 |
|
|
} else if ((iw & 0xf000) == 0x4000) { |
| 377 |
|
|
print_spaces(len); |
| 378 |
|
|
rd = ((iw >> 4) & 15) + 16; |
| 379 |
|
|
imm = ((iw >> 4) & 0xf0) + (iw & 15); |
| 380 |
|
|
debug("sbci\tr%i,0x%x\n", rd, imm); |
| 381 |
|
|
} else if ((iw & 0xf000) == 0x5000) { |
| 382 |
|
|
print_spaces(len); |
| 383 |
|
|
rd = ((iw >> 4) & 15) + 16; |
| 384 |
|
|
imm = ((iw >> 4) & 0xf0) + (iw & 15); |
| 385 |
|
|
debug("subi\tr%i,0x%x\n", rd, imm); |
| 386 |
|
|
} else if ((iw & 0xe000) == 0x6000) { |
| 387 |
|
|
print_spaces(len); |
| 388 |
|
|
rd = ((iw >> 4) & 15) + 16; |
| 389 |
|
|
imm = ((iw >> 4) & 0xf0) + (iw & 15); |
| 390 |
|
|
debug("%s\tr%i,0x%x\n", iw & 0x1000? "andi" : "ori", rd, imm); |
| 391 |
dpavlin |
14 |
} else if ((iw & 0xfe0f) == 0x8000) { |
| 392 |
|
|
print_spaces(len); |
| 393 |
|
|
rd = (iw >> 4) & 31; |
| 394 |
|
|
debug("ld\tr%i,Z\n", rd); |
| 395 |
|
|
} else if ((iw & 0xfe0f) == 0x8008) { |
| 396 |
|
|
print_spaces(len); |
| 397 |
|
|
rd = (iw >> 4) & 31; |
| 398 |
|
|
debug("ld\tr%i,Y\n", rd); |
| 399 |
dpavlin |
24 |
} else if ((iw & 0xfe0f) == 0x8208) { |
| 400 |
|
|
print_spaces(len); |
| 401 |
|
|
rd = (iw >> 4) & 31; |
| 402 |
|
|
debug("st\tY,r%i\n", rd); |
| 403 |
dpavlin |
14 |
} else if ((iw & 0xfe0f) == 0x900c) { |
| 404 |
|
|
print_spaces(len); |
| 405 |
|
|
rd = (iw >> 4) & 31; |
| 406 |
|
|
debug("ld\tr%i,X\n", rd); |
| 407 |
|
|
} else if ((iw & 0xfc0f) == 0x900f) { |
| 408 |
|
|
print_spaces(len); |
| 409 |
|
|
rd = (iw >> 4) & 31; |
| 410 |
|
|
debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd); |
| 411 |
dpavlin |
24 |
} else if ((iw & 0xfe0f) == 0x9000) { |
| 412 |
dpavlin |
14 |
print_two(ib, &len); |
| 413 |
|
|
addr = (ib[3] << 8) + ib[2]; |
| 414 |
|
|
print_spaces(len); |
| 415 |
dpavlin |
24 |
if (iw & 0x200) |
| 416 |
|
|
debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4); |
| 417 |
|
|
else |
| 418 |
|
|
debug("lds\tr%i,0x%x\n", (iw & 0x1f0) >> 4, addr); |
| 419 |
|
|
} else if ((iw & 0xfe0f) == 0x9209) { |
| 420 |
|
|
print_spaces(len); |
| 421 |
|
|
rr = (iw >> 4) & 31; |
| 422 |
|
|
debug("st\tY+,r%i\n", rr); |
| 423 |
|
|
} else if ((iw & 0xfe0f) == 0x920a) { |
| 424 |
|
|
print_spaces(len); |
| 425 |
|
|
rr = (iw >> 4) & 31; |
| 426 |
|
|
debug("st\t-Y,r%i\n", rr); |
| 427 |
|
|
} else if ((iw & 0xfe0f) == 0x9401) { |
| 428 |
|
|
print_spaces(len); |
| 429 |
|
|
rd = (iw >> 4) & 31; |
| 430 |
|
|
debug("neg\tr%i\n", rd); |
| 431 |
dpavlin |
14 |
} else if ((iw & 0xfe0f) == 0x9402) { |
| 432 |
|
|
print_spaces(len); |
| 433 |
|
|
rd = (iw >> 4) & 31; |
| 434 |
|
|
debug("swap\tr%i\n", rd); |
| 435 |
dpavlin |
24 |
} else if ((iw & 0xfe0f) == 0x9403) { |
| 436 |
|
|
print_spaces(len); |
| 437 |
|
|
rd = (iw >> 4) & 31; |
| 438 |
|
|
debug("inc\tr%i\n", rd); |
| 439 |
dpavlin |
14 |
} else if ((iw & 0xff0f) == 0x9408) { |
| 440 |
|
|
print_spaces(len); |
| 441 |
|
|
rd = (iw >> 4) & 7; |
| 442 |
|
|
debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]); |
| 443 |
dpavlin |
24 |
} else if ((iw & 0xfe0f) == 0x940a) { |
| 444 |
|
|
print_spaces(len); |
| 445 |
|
|
rd = (iw >> 4) & 31; |
| 446 |
|
|
debug("dec\tr%i\n", rd); |
| 447 |
|
|
} else if ((iw & 0xff8f) == 0x9408) { |
| 448 |
|
|
print_spaces(len); |
| 449 |
|
|
debug("bset\t%i\n", (iw >> 4) & 7); |
| 450 |
|
|
} else if ((iw & 0xff8f) == 0x9488) { |
| 451 |
|
|
print_spaces(len); |
| 452 |
|
|
debug("bclr\t%i\n", (iw >> 4) & 7); |
| 453 |
dpavlin |
14 |
} else if ((iw & 0xffef) == 0x9508) { |
| 454 |
|
|
/* ret and reti */ |
| 455 |
|
|
print_spaces(len); |
| 456 |
|
|
debug("ret%s\n", (iw & 0x10)? "i" : ""); |
| 457 |
|
|
} else if ((iw & 0xffff) == 0x9588) { |
| 458 |
|
|
print_spaces(len); |
| 459 |
|
|
debug("sleep\n"); |
| 460 |
dpavlin |
24 |
} else if ((iw & 0xffff) == 0x9598) { |
| 461 |
|
|
print_spaces(len); |
| 462 |
|
|
debug("break\n"); |
| 463 |
dpavlin |
14 |
} else if ((iw & 0xffff) == 0x95a8) { |
| 464 |
|
|
print_spaces(len); |
| 465 |
|
|
debug("wdr\n"); |
| 466 |
dpavlin |
24 |
} else if ((iw & 0xffef) == 0x95c8) { |
| 467 |
|
|
print_spaces(len); |
| 468 |
|
|
debug("%slpm\n", iw & 0x0010? "e" : ""); |
| 469 |
dpavlin |
14 |
} else if ((iw & 0xff00) == 0x9600) { |
| 470 |
|
|
print_spaces(len); |
| 471 |
|
|
imm = ((iw & 0xc0) >> 2) | (iw & 0xf); |
| 472 |
|
|
rd = ((iw >> 4) & 3) * 2 + 24; |
| 473 |
|
|
debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm); |
| 474 |
dpavlin |
24 |
} else if ((iw & 0xfd00) == 0x9800) { |
| 475 |
|
|
print_spaces(len); |
| 476 |
|
|
imm = iw & 7; |
| 477 |
|
|
rd = (iw >> 3) & 31; /* A */ |
| 478 |
|
|
debug("%sbi\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm); |
| 479 |
|
|
} else if ((iw & 0xfd00) == 0x9900) { |
| 480 |
|
|
print_spaces(len); |
| 481 |
|
|
imm = iw & 7; |
| 482 |
|
|
rd = (iw >> 3) & 31; /* A */ |
| 483 |
|
|
debug("sbi%s\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm); |
| 484 |
|
|
} else if ((iw & 0xf000) == 0xb000) { |
| 485 |
|
|
print_spaces(len); |
| 486 |
|
|
imm = ((iw & 0x600) >> 5) | (iw & 0xf); |
| 487 |
|
|
rr = (iw >> 4) & 31; |
| 488 |
|
|
if (iw & 0x800) |
| 489 |
|
|
debug("out\t0x%x,r%i\n", imm, rr); |
| 490 |
|
|
else |
| 491 |
|
|
debug("in\tr%i,0x%x\n", rr, imm); |
| 492 |
dpavlin |
14 |
} else if ((iw & 0xe000) == 0xc000) { |
| 493 |
|
|
print_spaces(len); |
| 494 |
|
|
addr = (int16_t)((iw & 0xfff) << 4); |
| 495 |
|
|
addr = (addr >> 3) + dumpaddr + 2; |
| 496 |
|
|
debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr); |
| 497 |
|
|
} else if ((iw & 0xf000) == 0xe000) { |
| 498 |
|
|
print_spaces(len); |
| 499 |
|
|
rd = ((iw >> 4) & 0xf) + 16; |
| 500 |
|
|
imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
| 501 |
|
|
debug("ldi\tr%i,0x%x\n", rd, imm); |
| 502 |
dpavlin |
24 |
} else if ((iw & 0xfc00) == 0xf000) { |
| 503 |
|
|
print_spaces(len); |
| 504 |
|
|
addr = (iw >> 3) & 0x7f; |
| 505 |
|
|
if (addr >= 64) |
| 506 |
|
|
addr -= 128; |
| 507 |
|
|
addr = (addr + 1) * 2 + dumpaddr; |
| 508 |
|
|
debug("brbs\t%c,0x%x\n", sreg_names[iw & 7], addr); |
| 509 |
|
|
} else if ((iw & 0xfc00) == 0xf400) { |
| 510 |
|
|
print_spaces(len); |
| 511 |
|
|
addr = (iw >> 3) & 0x7f; |
| 512 |
|
|
if (addr >= 64) |
| 513 |
|
|
addr -= 128; |
| 514 |
|
|
addr = (addr + 1) * 2 + dumpaddr; |
| 515 |
|
|
debug("brbc\t%c,0x%x\n", sreg_names[iw & 7], addr); |
| 516 |
|
|
} else if ((iw & 0xfc08) == 0xfc00) { |
| 517 |
|
|
print_spaces(len); |
| 518 |
|
|
rr = (iw >> 4) & 31; |
| 519 |
|
|
imm = iw & 7; |
| 520 |
|
|
debug("sbr%s\tr%i,%i\n", iw & 0x0200 ? "s" : "c", rr, imm); |
| 521 |
dpavlin |
14 |
} else { |
| 522 |
|
|
print_spaces(len); |
| 523 |
|
|
debug("UNIMPLEMENTED 0x%04x\n", iw); |
| 524 |
|
|
} |
| 525 |
|
|
|
| 526 |
|
|
return len; |
| 527 |
|
|
} |
| 528 |
|
|
|
| 529 |
|
|
|
| 530 |
|
|
#include "tmp_avr_tail.c" |
| 531 |
|
|
|
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