/[gxemul]/trunk/src/cpus/cpu_avr.c
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Revision 24 - (hide annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 15222 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============
1 dpavlin 14 /*
2 dpavlin 24 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 24 * $Id: cpu_avr.c,v 1.18 2006/06/16 18:31:25 debug Exp $
29 dpavlin 14 *
30     * Atmel AVR (8-bit) CPU emulation.
31     */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36     #include <ctype.h>
37    
38     #include "cpu.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42     #include "symbol.h"
43    
44    
45     #define DYNTRANS_32
46 dpavlin 20 #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
47 dpavlin 14 #include "tmp_avr_head.c"
48    
49    
50     /*
51     * avr_cpu_new():
52     *
53     * Create a new AVR cpu object.
54     *
55     * Returns 1 on success, 0 if there was no matching AVR processor with
56     * this cpu_type_name.
57     */
58     int avr_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
59     int cpu_id, char *cpu_type_name)
60     {
61 dpavlin 24 int type = 0;
62    
63     if (strcasecmp(cpu_type_name, "AVR") == 0 ||
64     strcasecmp(cpu_type_name, "AVR16") == 0 ||
65     strcasecmp(cpu_type_name, "AT90S2313") == 0 ||
66     strcasecmp(cpu_type_name, "AT90S8515") == 0)
67     type = 16;
68     if (strcasecmp(cpu_type_name, "AVR22") == 0)
69     type = 22;
70    
71     if (type == 0)
72 dpavlin 14 return 0;
73    
74     cpu->memory_rw = avr_memory_rw;
75     cpu->update_translation_table = avr_update_translation_table;
76 dpavlin 18 cpu->invalidate_translation_caches =
77     avr_invalidate_translation_caches;
78 dpavlin 14 cpu->invalidate_code_translation = avr_invalidate_code_translation;
79     cpu->is_32bit = 1;
80    
81     cpu->byte_order = EMUL_LITTLE_ENDIAN;
82    
83 dpavlin 24 cpu->cd.avr.is_22bit = (type == 22);
84     cpu->cd.avr.pc_mask = cpu->cd.avr.is_22bit? 0x3fffff : 0xffff;
85 dpavlin 14
86 dpavlin 24 cpu->cd.avr.sram_mask = 0xff; /* 256 bytes ram */
87     cpu->cd.avr.sp = cpu->cd.avr.sram_mask - 2;
88    
89 dpavlin 14 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
90     if (cpu_id == 0) {
91     debug("%s", cpu->name);
92     }
93    
94     return 1;
95     }
96    
97    
98     /*
99     * avr_cpu_list_available_types():
100     *
101     * Print a list of available AVR CPU types.
102     */
103     void avr_cpu_list_available_types(void)
104     {
105 dpavlin 24 debug("AVR\tAVR16\tAVR22\n");
106 dpavlin 14 }
107    
108    
109     /*
110     * avr_cpu_dumpinfo():
111     */
112     void avr_cpu_dumpinfo(struct cpu *cpu)
113     {
114 dpavlin 24 debug(" (%i-bit program counter)\n",
115     cpu->cd.avr.is_22bit? 22 : 16);
116 dpavlin 14 }
117    
118    
119     /*
120     * avr_cpu_register_dump():
121     *
122     * Dump cpu registers in a relatively readable format.
123     *
124     * gprs: set to non-zero to dump GPRs and some special-purpose registers.
125     * coprocs: set bit 0..3 to dump registers in coproc 0..3.
126     */
127     void avr_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
128     {
129     char *symbol;
130     uint64_t offset;
131     int i, x = cpu->cpu_id;
132    
133     if (gprs) {
134     /* Special registers (pc, ...) first: */
135     symbol = get_symbol_name(&cpu->machine->symbol_context,
136     cpu->pc, &offset);
137    
138     debug("cpu%i: sreg = ", x);
139     debug("%c", cpu->cd.avr.sreg & AVR_SREG_I? 'I' : 'i');
140     debug("%c", cpu->cd.avr.sreg & AVR_SREG_T? 'T' : 't');
141     debug("%c", cpu->cd.avr.sreg & AVR_SREG_H? 'H' : 'h');
142     debug("%c", cpu->cd.avr.sreg & AVR_SREG_S? 'S' : 's');
143     debug("%c", cpu->cd.avr.sreg & AVR_SREG_V? 'V' : 'v');
144     debug("%c", cpu->cd.avr.sreg & AVR_SREG_N? 'N' : 'n');
145     debug("%c", cpu->cd.avr.sreg & AVR_SREG_Z? 'Z' : 'z');
146     debug("%c", cpu->cd.avr.sreg & AVR_SREG_C? 'C' : 'c');
147 dpavlin 24 if (cpu->cd.avr.is_22bit)
148     debug(" pc = 0x%06x", (int)cpu->pc);
149     else
150     debug(" pc = 0x%04x", (int)cpu->pc);
151 dpavlin 14 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
152    
153     for (i=0; i<N_AVR_REGS; i++) {
154 dpavlin 24 int r = (i >> 3) + ((i & 7) << 2);
155     if ((i % 8) == 0)
156     debug("cpu%i:", x);
157     debug(" r%02i=0x%02x", r, cpu->cd.avr.r[r]);
158     if ((i % 8) == 7)
159     debug("\n");
160 dpavlin 14 }
161 dpavlin 24
162     debug("cpu%i: x=%i, y=%i, z=%i, sp=0x%04x\n", x,
163     (int)(int16_t)(cpu->cd.avr.r[27]*256 + cpu->cd.avr.r[26]),
164     (int)(int16_t)(cpu->cd.avr.r[29]*256 + cpu->cd.avr.r[28]),
165     (int)(int16_t)(cpu->cd.avr.r[31]*256 + cpu->cd.avr.r[30]),
166     cpu->cd.avr.sp);
167 dpavlin 14 }
168    
169     debug("cpu%i: nr of instructions: %lli\n", x,
170     (long long)cpu->machine->ncycles);
171     debug("cpu%i: nr of cycles: %lli\n", x,
172     (long long)(cpu->machine->ncycles + cpu->cd.avr.extra_cycles));
173     }
174    
175    
176     /*
177     * avr_cpu_register_match():
178     */
179     void avr_cpu_register_match(struct machine *m, char *name,
180     int writeflag, uint64_t *valuep, int *match_register)
181     {
182     int cpunr = 0;
183    
184     /* CPU number: */
185     /* TODO */
186    
187     if (strcasecmp(name, "pc") == 0) {
188     if (writeflag) {
189     m->cpus[cpunr]->pc = *valuep;
190     } else
191     *valuep = m->cpus[cpunr]->pc;
192     *match_register = 1;
193     } else if (name[0] == 'r' && isdigit((int)name[1])) {
194     int nr = atoi(name + 1);
195     if (nr >= 0 && nr < N_AVR_REGS) {
196     if (writeflag)
197     m->cpus[cpunr]->cd.avr.r[nr] = *valuep;
198     else
199     *valuep = m->cpus[cpunr]->cd.avr.r[nr];
200     *match_register = 1;
201     }
202     }
203     }
204    
205    
206     /*
207 dpavlin 24 * avr_cpu_tlbdump():
208     *
209     * Called from the debugger to dump the TLB in a readable format.
210     * x is the cpu number to dump, or -1 to dump all CPUs.
211     *
212     * If rawflag is nonzero, then the TLB contents isn't formated nicely,
213     * just dumped.
214     */
215     void avr_cpu_tlbdump(struct machine *m, int x, int rawflag)
216     {
217     }
218    
219    
220     /*
221     * avr_cpu_gdb_stub():
222     *
223     * Execute a "remote GDB" command. Returns a newly allocated response string
224     * on success, NULL on failure.
225     */
226     char *avr_cpu_gdb_stub(struct cpu *cpu, char *cmd)
227     {
228     fatal("avr_cpu_gdb_stub(): TODO\n");
229     return NULL;
230     }
231    
232    
233     /*
234 dpavlin 14 * avr_cpu_interrupt():
235     */
236     int avr_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
237     {
238     fatal("avr_cpu_interrupt(): TODO\n");
239     return 0;
240     }
241    
242    
243     /*
244     * avr_cpu_interrupt_ack():
245     */
246     int avr_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
247     {
248     /* fatal("avr_cpu_interrupt_ack(): TODO\n"); */
249     return 0;
250     }
251    
252    
253     /* Helper functions: */
254     static void print_two(unsigned char *instr, int *len)
255     { debug(" %02x %02x", instr[*len], instr[*len+1]); (*len) += 2; }
256     static void print_spaces(int len) { int i; debug(" "); for (i=0; i<15-len/2*6;
257     i++) debug(" "); }
258    
259    
260     /*
261     * avr_cpu_disassemble_instr():
262     *
263     * Convert an instruction word into human readable format, for instruction
264     * tracing and disassembly.
265     *
266     * If running is 1, cpu->pc should be the address of the instruction.
267     *
268     * If running is 0, things that depend on the runtime environment (eg.
269     * register contents) will not be shown, and addr will be used instead of
270     * cpu->pc for relative addresses.
271     */
272     int avr_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
273 dpavlin 24 int running, uint64_t dumpaddr)
274 dpavlin 14 {
275     uint64_t offset;
276     int len = 0, addr, iw, rd, rr, imm;
277     char *symbol;
278     char *sreg_names = SREG_NAMES;
279    
280     if (running)
281     dumpaddr = cpu->pc;
282    
283     symbol = get_symbol_name(&cpu->machine->symbol_context,
284     dumpaddr, &offset);
285     if (symbol != NULL && offset==0)
286     debug("<%s>\n", symbol);
287    
288     if (cpu->machine->ncpus > 1 && running)
289     debug("cpu%i: ", cpu->cpu_id);
290    
291     /* TODO: 22-bit PC */
292     debug("0x%04x: ", (int)dumpaddr);
293    
294     print_two(ib, &len);
295     iw = (ib[1] << 8) + ib[0];
296    
297     if ((iw & 0xffff) == 0x0000) {
298     print_spaces(len);
299     debug("nop\n");
300 dpavlin 24 } else if ((iw & 0xff00) == 0x0100) {
301 dpavlin 14 print_spaces(len);
302 dpavlin 24 rd = (iw >> 3) & 30;
303     rr = (iw << 1) & 30;
304     debug("movw\tr%i:r%i,r%i:r%i\n", rd+1, rd, rr+1, rr);
305     } else if ((iw & 0xff00) == 0x0200) {
306     print_spaces(len);
307     rd = ((iw >> 4) & 15) + 16;
308     rr = (iw & 15) + 16;
309     debug("muls\tr%i,r%i\n", rd, rr);
310     } else if ((iw & 0xff88) == 0x0300) {
311     print_spaces(len);
312     rd = ((iw >> 4) & 7) + 16;
313     rr = (iw & 7) + 16;
314     debug("mulsu\tr%i,r%i\n", rd, rr);
315     } else if ((iw & 0xff88) == 0x0308) {
316     print_spaces(len);
317     rd = ((iw >> 4) & 7) + 16;
318     rr = (iw & 7) + 16;
319     debug("fmul\tr%i,r%i\n", rd, rr);
320     } else if ((iw & 0xff88) == 0x0380) {
321     print_spaces(len);
322     rd = ((iw >> 4) & 7) + 16;
323     rr = (iw & 7) + 16;
324     debug("fmuls\tr%i,r%i\n", rd, rr);
325     } else if ((iw & 0xff88) == 0x0388) {
326     print_spaces(len);
327     rd = ((iw >> 4) & 7) + 16;
328     rr = (iw & 7) + 16;
329     debug("fmulsu\tr%i,r%i\n", rd, rr);
330     } else if ((iw & 0xec00) == 0x0400) {
331     print_spaces(len);
332 dpavlin 14 rd = (iw & 0x1f0) >> 4;
333     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
334 dpavlin 24 debug("cp%s\tr%i,r%i\n", iw & 0x1000? "" : "c", rd, rr);
335     } else if ((iw & 0xec00) == 0x0800) {
336 dpavlin 14 print_spaces(len);
337     rd = (iw & 0x1f0) >> 4;
338     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
339 dpavlin 24 debug("%s\tr%i,r%i\n", iw & 0x1000? "sub" : "sbc", rd, rr);
340     } else if ((iw & 0xec00) == 0x0c00) {
341     print_spaces(len);
342     rd = (iw & 0x1f0) >> 4;
343     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
344     debug("%s\tr%i,r%i\n", iw & 0x1000? "adc" : "add", rd, rr);
345     } else if ((iw & 0xfc00) == 0x1000) {
346     print_spaces(len);
347     rd = (iw & 0x1f0) >> 4;
348     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
349     debug("cpse\tr%i,r%i\n", rd, rr);
350 dpavlin 14 } else if ((iw & 0xfc00) == 0x2000) {
351     print_spaces(len);
352     rd = (iw & 0x1f0) >> 4;
353     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
354     debug("and\tr%i,r%i\n", rd, rr);
355 dpavlin 24 } else if ((iw & 0xfc00) == 0x2400) {
356     print_spaces(len);
357     rd = (iw & 0x1f0) >> 4;
358     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
359     debug("eor\tr%i,r%i\n", rd, rr);
360     } else if ((iw & 0xfc00) == 0x2800) {
361     print_spaces(len);
362     rd = (iw & 0x1f0) >> 4;
363     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
364     debug("or\tr%i,r%i\n", rd, rr);
365 dpavlin 14 } else if ((iw & 0xfc00) == 0x2c00) {
366     print_spaces(len);
367     rd = (iw & 0x1f0) >> 4;
368     rr = ((iw & 0x200) >> 5) | (iw & 0xf);
369     debug("mov\tr%i,r%i\n", rd, rr);
370 dpavlin 24 } else if ((iw & 0xf000) == 0x3000) {
371     print_spaces(len);
372     rd = ((iw >> 4) & 15) + 16;
373     imm = ((iw >> 4) & 0xf0) + (iw & 15);
374     debug("cpi\tr%i,0x%x\n", rd, imm);
375     } else if ((iw & 0xf000) == 0x4000) {
376     print_spaces(len);
377     rd = ((iw >> 4) & 15) + 16;
378     imm = ((iw >> 4) & 0xf0) + (iw & 15);
379     debug("sbci\tr%i,0x%x\n", rd, imm);
380     } else if ((iw & 0xf000) == 0x5000) {
381     print_spaces(len);
382     rd = ((iw >> 4) & 15) + 16;
383     imm = ((iw >> 4) & 0xf0) + (iw & 15);
384     debug("subi\tr%i,0x%x\n", rd, imm);
385     } else if ((iw & 0xe000) == 0x6000) {
386     print_spaces(len);
387     rd = ((iw >> 4) & 15) + 16;
388     imm = ((iw >> 4) & 0xf0) + (iw & 15);
389     debug("%s\tr%i,0x%x\n", iw & 0x1000? "andi" : "ori", rd, imm);
390 dpavlin 14 } else if ((iw & 0xfe0f) == 0x8000) {
391     print_spaces(len);
392     rd = (iw >> 4) & 31;
393     debug("ld\tr%i,Z\n", rd);
394     } else if ((iw & 0xfe0f) == 0x8008) {
395     print_spaces(len);
396     rd = (iw >> 4) & 31;
397     debug("ld\tr%i,Y\n", rd);
398 dpavlin 24 } else if ((iw & 0xfe0f) == 0x8208) {
399     print_spaces(len);
400     rd = (iw >> 4) & 31;
401     debug("st\tY,r%i\n", rd);
402 dpavlin 14 } else if ((iw & 0xfe0f) == 0x900c) {
403     print_spaces(len);
404     rd = (iw >> 4) & 31;
405     debug("ld\tr%i,X\n", rd);
406     } else if ((iw & 0xfc0f) == 0x900f) {
407     print_spaces(len);
408     rd = (iw >> 4) & 31;
409     debug("%s\tr%i\n", iw & 0x200? "push" : "pop", rd);
410 dpavlin 24 } else if ((iw & 0xfe0f) == 0x9000) {
411 dpavlin 14 print_two(ib, &len);
412     addr = (ib[3] << 8) + ib[2];
413     print_spaces(len);
414 dpavlin 24 if (iw & 0x200)
415     debug("sts\t0x%x,r%i\n", addr, (iw & 0x1f0) >> 4);
416     else
417     debug("lds\tr%i,0x%x\n", (iw & 0x1f0) >> 4, addr);
418     } else if ((iw & 0xfe0f) == 0x9209) {
419     print_spaces(len);
420     rr = (iw >> 4) & 31;
421     debug("st\tY+,r%i\n", rr);
422     } else if ((iw & 0xfe0f) == 0x920a) {
423     print_spaces(len);
424     rr = (iw >> 4) & 31;
425     debug("st\t-Y,r%i\n", rr);
426     } else if ((iw & 0xfe0f) == 0x9401) {
427     print_spaces(len);
428     rd = (iw >> 4) & 31;
429     debug("neg\tr%i\n", rd);
430 dpavlin 14 } else if ((iw & 0xfe0f) == 0x9402) {
431     print_spaces(len);
432     rd = (iw >> 4) & 31;
433     debug("swap\tr%i\n", rd);
434 dpavlin 24 } else if ((iw & 0xfe0f) == 0x9403) {
435     print_spaces(len);
436     rd = (iw >> 4) & 31;
437     debug("inc\tr%i\n", rd);
438 dpavlin 14 } else if ((iw & 0xff0f) == 0x9408) {
439     print_spaces(len);
440     rd = (iw >> 4) & 7;
441     debug("%s%c\n", iw & 0x80? "cl" : "se", sreg_names[rd]);
442 dpavlin 24 } else if ((iw & 0xfe0f) == 0x940a) {
443     print_spaces(len);
444     rd = (iw >> 4) & 31;
445     debug("dec\tr%i\n", rd);
446     } else if ((iw & 0xff8f) == 0x9408) {
447     print_spaces(len);
448     debug("bset\t%i\n", (iw >> 4) & 7);
449     } else if ((iw & 0xff8f) == 0x9488) {
450     print_spaces(len);
451     debug("bclr\t%i\n", (iw >> 4) & 7);
452 dpavlin 14 } else if ((iw & 0xffef) == 0x9508) {
453     /* ret and reti */
454     print_spaces(len);
455     debug("ret%s\n", (iw & 0x10)? "i" : "");
456     } else if ((iw & 0xffff) == 0x9588) {
457     print_spaces(len);
458     debug("sleep\n");
459 dpavlin 24 } else if ((iw & 0xffff) == 0x9598) {
460     print_spaces(len);
461     debug("break\n");
462 dpavlin 14 } else if ((iw & 0xffff) == 0x95a8) {
463     print_spaces(len);
464     debug("wdr\n");
465 dpavlin 24 } else if ((iw & 0xffef) == 0x95c8) {
466     print_spaces(len);
467     debug("%slpm\n", iw & 0x0010? "e" : "");
468 dpavlin 14 } else if ((iw & 0xff00) == 0x9600) {
469     print_spaces(len);
470     imm = ((iw & 0xc0) >> 2) | (iw & 0xf);
471     rd = ((iw >> 4) & 3) * 2 + 24;
472     debug("adiw\tr%i:r%i,0x%x\n", rd, rd+1, imm);
473 dpavlin 24 } else if ((iw & 0xfd00) == 0x9800) {
474     print_spaces(len);
475     imm = iw & 7;
476     rd = (iw >> 3) & 31; /* A */
477     debug("%sbi\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm);
478     } else if ((iw & 0xfd00) == 0x9900) {
479     print_spaces(len);
480     imm = iw & 7;
481     rd = (iw >> 3) & 31; /* A */
482     debug("sbi%s\t0x%x,%i\n", iw & 0x0200? "s" : "c", rd, imm);
483     } else if ((iw & 0xf000) == 0xb000) {
484     print_spaces(len);
485     imm = ((iw & 0x600) >> 5) | (iw & 0xf);
486     rr = (iw >> 4) & 31;
487     if (iw & 0x800)
488     debug("out\t0x%x,r%i\n", imm, rr);
489     else
490     debug("in\tr%i,0x%x\n", rr, imm);
491 dpavlin 14 } else if ((iw & 0xe000) == 0xc000) {
492     print_spaces(len);
493     addr = (int16_t)((iw & 0xfff) << 4);
494     addr = (addr >> 3) + dumpaddr + 2;
495     debug("%s\t0x%x\n", iw & 0x1000? "rcall" : "rjmp", addr);
496     } else if ((iw & 0xf000) == 0xe000) {
497     print_spaces(len);
498     rd = ((iw >> 4) & 0xf) + 16;
499     imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
500     debug("ldi\tr%i,0x%x\n", rd, imm);
501 dpavlin 24 } else if ((iw & 0xfc00) == 0xf000) {
502     print_spaces(len);
503     addr = (iw >> 3) & 0x7f;
504     if (addr >= 64)
505     addr -= 128;
506     addr = (addr + 1) * 2 + dumpaddr;
507     debug("brbs\t%c,0x%x\n", sreg_names[iw & 7], addr);
508     } else if ((iw & 0xfc00) == 0xf400) {
509     print_spaces(len);
510     addr = (iw >> 3) & 0x7f;
511     if (addr >= 64)
512     addr -= 128;
513     addr = (addr + 1) * 2 + dumpaddr;
514     debug("brbc\t%c,0x%x\n", sreg_names[iw & 7], addr);
515     } else if ((iw & 0xfc08) == 0xfc00) {
516     print_spaces(len);
517     rr = (iw >> 4) & 31;
518     imm = iw & 7;
519     debug("sbr%s\tr%i,%i\n", iw & 0x0200 ? "s" : "c", rr, imm);
520 dpavlin 14 } else {
521     print_spaces(len);
522     debug("UNIMPLEMENTED 0x%04x\n", iw);
523     }
524    
525     return len;
526     }
527    
528    
529     #include "tmp_avr_tail.c"
530    
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