/[gxemul]/trunk/src/cpus/cpu_arm_instr_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Diff of /trunk/src/cpus/cpu_arm_instr_misc.c

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revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: cpu_arm_instr_misc.c,v 1.1 2005/10/25 08:53:21 debug Exp $   *  $Id: cpu_arm_instr_misc.c,v 1.5 2006/04/02 10:21:08 debug Exp $
29   *   *
30   *  Misc ARM instructions. Included from cpu_arm_instr.c.   *  Misc ARM instructions. Included from cpu_arm_instr.c.
31   */   */
# Line 70  X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y Line 70  X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y
70  X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)  X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)
71  X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)  X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)
72    
73    
74    /*
75     *  add1_rX: Add #1 to a register. (Optimization hack.)
76     */
77    X(add1_r0)  { cpu->cd.arm.r[ 0] ++; } Y(add1_r0)
78    X(add1_r1)  { cpu->cd.arm.r[ 1] ++; } Y(add1_r1)
79    X(add1_r2)  { cpu->cd.arm.r[ 2] ++; } Y(add1_r2)
80    X(add1_r3)  { cpu->cd.arm.r[ 3] ++; } Y(add1_r3)
81    X(add1_r4)  { cpu->cd.arm.r[ 4] ++; } Y(add1_r4)
82    X(add1_r5)  { cpu->cd.arm.r[ 5] ++; } Y(add1_r5)
83    X(add1_r6)  { cpu->cd.arm.r[ 6] ++; } Y(add1_r6)
84    X(add1_r7)  { cpu->cd.arm.r[ 7] ++; } Y(add1_r7)
85    X(add1_r8)  { cpu->cd.arm.r[ 8] ++; } Y(add1_r8)
86    X(add1_r9)  { cpu->cd.arm.r[ 9] ++; } Y(add1_r9)
87    X(add1_r10) { cpu->cd.arm.r[10] ++; } Y(add1_r10)
88    X(add1_r11) { cpu->cd.arm.r[11] ++; } Y(add1_r11)
89    X(add1_r12) { cpu->cd.arm.r[12] ++; } Y(add1_r12)
90    X(add1_r13) { cpu->cd.arm.r[13] ++; } Y(add1_r13)
91    X(add1_r14) { cpu->cd.arm.r[14] ++; } Y(add1_r14)
92    
93    
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