/[gxemul]/trunk/src/cpus/cpu_arm_instr_misc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/cpu_arm_instr_misc.c

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Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (13 years, 1 month ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 dpavlin 18 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: cpu_arm_instr_misc.c,v 1.1 2005/10/25 08:53:21 debug Exp $
29     *
30     * Misc ARM instructions. Included from cpu_arm_instr.c.
31     */
32    
33    
34     /*
35     * clear_rX: Move #0 into a register. (Optimization hack.)
36     */
37     X(clear_r0) { cpu->cd.arm.r[ 0] = 0; } Y(clear_r0)
38     X(clear_r1) { cpu->cd.arm.r[ 1] = 0; } Y(clear_r1)
39     X(clear_r2) { cpu->cd.arm.r[ 2] = 0; } Y(clear_r2)
40     X(clear_r3) { cpu->cd.arm.r[ 3] = 0; } Y(clear_r3)
41     X(clear_r4) { cpu->cd.arm.r[ 4] = 0; } Y(clear_r4)
42     X(clear_r5) { cpu->cd.arm.r[ 5] = 0; } Y(clear_r5)
43     X(clear_r6) { cpu->cd.arm.r[ 6] = 0; } Y(clear_r6)
44     X(clear_r7) { cpu->cd.arm.r[ 7] = 0; } Y(clear_r7)
45     X(clear_r8) { cpu->cd.arm.r[ 8] = 0; } Y(clear_r8)
46     X(clear_r9) { cpu->cd.arm.r[ 9] = 0; } Y(clear_r9)
47     X(clear_r10) { cpu->cd.arm.r[10] = 0; } Y(clear_r10)
48     X(clear_r11) { cpu->cd.arm.r[11] = 0; } Y(clear_r11)
49     X(clear_r12) { cpu->cd.arm.r[12] = 0; } Y(clear_r12)
50     X(clear_r13) { cpu->cd.arm.r[13] = 0; } Y(clear_r13)
51     X(clear_r14) { cpu->cd.arm.r[14] = 0; } Y(clear_r14)
52    
53    
54     /*
55     * mov1_rX: Move #1 into a register. (Optimization hack.)
56     */
57     X(mov1_r0) { cpu->cd.arm.r[ 0] = 1; } Y(mov1_r0)
58     X(mov1_r1) { cpu->cd.arm.r[ 1] = 1; } Y(mov1_r1)
59     X(mov1_r2) { cpu->cd.arm.r[ 2] = 1; } Y(mov1_r2)
60     X(mov1_r3) { cpu->cd.arm.r[ 3] = 1; } Y(mov1_r3)
61     X(mov1_r4) { cpu->cd.arm.r[ 4] = 1; } Y(mov1_r4)
62     X(mov1_r5) { cpu->cd.arm.r[ 5] = 1; } Y(mov1_r5)
63     X(mov1_r6) { cpu->cd.arm.r[ 6] = 1; } Y(mov1_r6)
64     X(mov1_r7) { cpu->cd.arm.r[ 7] = 1; } Y(mov1_r7)
65     X(mov1_r8) { cpu->cd.arm.r[ 8] = 1; } Y(mov1_r8)
66     X(mov1_r9) { cpu->cd.arm.r[ 9] = 1; } Y(mov1_r9)
67     X(mov1_r10) { cpu->cd.arm.r[10] = 1; } Y(mov1_r10)
68     X(mov1_r11) { cpu->cd.arm.r[11] = 1; } Y(mov1_r11)
69     X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y(mov1_r12)
70     X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13)
71     X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14)
72    

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