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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm_instr_loadstore.c,v 1.8 2005/10/05 21:17:32 debug Exp $ |
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* |
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* |
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* TODO: Many things... |
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* |
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* o) Big-endian ARM loads/stores. |
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* |
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* o) Alignment checks! |
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* |
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* o) Native load/store if the endianness is the same as the host's |
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* |
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* o) "Base Updated Abort Model", which updates the base register |
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* even if the memory access failed. |
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* |
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* o) Some ARM implementations use pc+8, some use pc+12 for stores? |
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* |
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* o) All load/store variants with the PC register are not really |
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* valid. (E.g. a byte load into the PC register. What should that |
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* accomplish?) |
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* |
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* o) Perhaps an optimization for the case when offset = 0, because |
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* that's quite common, and also when the Reg expression is just |
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* a simple, non-rotated register (0..14). |
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*/ |
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|
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|
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/* |
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* General load/store, by using memory_rw(). If at all possible, memory_rw() |
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* then inserts the page into the translation array, so that the fast |
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* load/store routine below can be used for further accesses. |
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*/ |
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void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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#if !defined(A__P) && defined(A__W) |
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const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS; |
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#else |
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const int memory_rw_flags = CACHE_DATA; |
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#endif |
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#ifdef A__B |
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unsigned char data[1]; |
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#else |
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#ifdef A__H |
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unsigned char data[2]; |
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#else |
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unsigned char data[4]; |
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#endif |
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#endif |
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uint32_t addr, low_pc, offset = |
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#ifndef A__U |
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- |
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#endif |
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#ifdef A__REG |
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R(cpu, ic, ic->arg[1], 0) |
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#else |
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ic->arg[1] |
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#endif |
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; |
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|
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low_pc = ((size_t)ic - (size_t)cpu->cd.arm. |
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cur_ic_page) / sizeof(struct arm_instr_call); |
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cpu->cd.arm.r[ARM_PC] &= ~((ARM_IC_ENTRIES_PER_PAGE-1) |
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<< ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->cd.arm.r[ARM_PC] += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc = cpu->cd.arm.r[ARM_PC]; |
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|
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addr = reg(ic->arg[0]) |
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#ifdef A__P |
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+ offset |
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#endif |
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; |
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|
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#ifdef A__L |
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/* Load: */ |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_READ, memory_rw_flags)) { |
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/* load failed, an exception was generated */ |
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return; |
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} |
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#ifdef A__B |
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reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
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(int32_t)(int8_t) |
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#endif |
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data[0]; |
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#else |
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#ifdef A__H |
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reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
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(int32_t)(int16_t) |
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#endif |
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(data[0] + (data[1] << 8)); |
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#else |
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reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
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(data[2] << 16) + (data[3] << 24); |
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#endif |
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#endif |
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#else |
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/* Store: */ |
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#ifdef A__B |
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data[0] = reg(ic->arg[2]); |
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#else |
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#ifdef A__H |
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data[0] = reg(ic->arg[2]); |
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data[1] = reg(ic->arg[2]) >> 8; |
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#else |
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data[0] = reg(ic->arg[2]); |
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data[1] = reg(ic->arg[2]) >> 8; |
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data[2] = reg(ic->arg[2]) >> 16; |
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data[3] = reg(ic->arg[2]) >> 24; |
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#endif |
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#endif |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_WRITE, memory_rw_flags)) { |
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/* store failed, an exception was generated */ |
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return; |
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} |
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#endif |
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|
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#ifdef A__P |
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#ifdef A__W |
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reg(ic->arg[0]) = addr; |
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#endif |
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#else /* post-index writeback */ |
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reg(ic->arg[0]) = addr + offset; |
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#endif |
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} |
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|
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|
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/* |
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* Fast load/store, if the page is in the translation array. |
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*/ |
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void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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#if !defined(A__P) && defined(A__W) |
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/* T-bit: userland access. Use the general routine for that. */ |
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A__NAME__general(cpu, ic); |
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#else |
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uint32_t offset = |
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#ifndef A__U |
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- |
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#endif |
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#ifdef A__REG |
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R(cpu, ic, ic->arg[1], 0) |
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#else |
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ic->arg[1] |
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#endif |
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; |
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uint32_t addr = reg(ic->arg[0]) |
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#ifdef A__P |
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+ offset |
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#endif |
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; |
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unsigned char *page = cpu->cd.arm. |
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#ifdef A__L |
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host_load |
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#else |
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host_store |
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#endif |
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[addr >> 12]; |
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|
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if (page == NULL) { |
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A__NAME__general(cpu, ic); |
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} else { |
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#ifdef A__L |
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#ifdef A__B |
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reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
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(int32_t)(int8_t) |
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#endif |
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page[addr & 0xfff]; |
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#else |
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#ifdef A__H |
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reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
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(int32_t)(int16_t) |
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#endif |
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(page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8)); |
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#else |
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reg(ic->arg[2]) = page[addr & 0xfff] + |
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(page[(addr & 0xfff) + 1] << 8) + |
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(page[(addr & 0xfff) + 2] << 16) + |
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(page[(addr & 0xfff) + 3] << 24); |
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#endif |
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#endif |
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#else |
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#ifdef A__B |
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page[addr & 0xfff] = reg(ic->arg[2]); |
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#else |
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#ifdef A__H |
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page[addr & 0xfff] = reg(ic->arg[2]); |
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page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
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#else |
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page[addr & 0xfff] = reg(ic->arg[2]); |
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page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
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page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16; |
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page[(addr & 0xfff)+3] = reg(ic->arg[2]) >> 24; |
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#endif |
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#endif |
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#endif |
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|
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/* Index Write-back: */ |
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#ifdef A__P |
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#ifdef A__W |
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reg(ic->arg[0]) = addr; |
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#endif |
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#else |
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/* post-index writeback */ |
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reg(ic->arg[0]) = addr + offset; |
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#endif |
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} |
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#endif /* not T-bit */ |
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} |
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|
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|
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/* |
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* Special case when loading or storing the ARM's PC register, or when the PC |
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* register is used as the base address register. |
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* |
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* o) Loads into the PC register cause a branch. If an exception occured |
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* during the load, then the PC register should already point to the |
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* exception handler, in which case we simply recalculate the pointers a |
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* second time (no harm is done by doing that). |
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* |
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* TODO: A tiny performance optimization would be to separate the two |
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* cases: a load where arg[0] = PC, and the case where arg[2] = PC. |
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* |
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* o) Stores store "PC of the current instruction + 12". The solution I have |
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* choosen is to calculate this value and place it into a temporary |
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* variable (tmp_pc), which is then used for the store. |
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*/ |
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void A__NAME_PC(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
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#ifdef A__L |
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/* Load: */ |
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if (ic->arg[0] == (size_t)(&cpu->cd.arm.tmp_pc)) { |
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/* tmp_pc = current PC + 8: */ |
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uint32_t low_pc, tmp; |
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low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
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sizeof(struct arm_instr_call); |
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tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
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ARM_INSTR_ALIGNMENT_SHIFT); |
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tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->cd.arm.tmp_pc = tmp + 8; |
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} |
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A__NAME(cpu, ic); |
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if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) { |
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cpu->pc = cpu->cd.arm.r[ARM_PC]; |
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arm_pc_to_pointers(cpu); |
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} |
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#else |
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/* Store: */ |
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uint32_t low_pc, tmp; |
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/* Calculate tmp from this instruction's PC + 12 */ |
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low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
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sizeof(struct arm_instr_call); |
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tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
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ARM_INSTR_ALIGNMENT_SHIFT); |
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tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->cd.arm.tmp_pc = tmp + 12; |
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A__NAME(cpu, ic); |
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#endif |
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} |
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|
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|
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#ifndef A__NOCONDITIONS |
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/* Load/stores with all registers except the PC register: */ |
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void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME(cpu, ic); } |
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void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME(cpu, ic); } |
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void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
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void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME(cpu, ic); } |
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void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME(cpu, ic); } |
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void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME(cpu, ic); } |
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void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME(cpu, ic); } |
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|
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void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
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!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
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!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
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void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
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void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
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void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
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!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
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(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
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|
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|
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/* Load/stores with the PC register: */ |
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void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME_PC(cpu, ic); } |
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|
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void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
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!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
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!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
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!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
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void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic) |
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{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
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((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
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(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
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#endif |
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