/[gxemul]/trunk/src/cpus/cpu_arm_instr_loadstore.c
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Contents of /trunk/src/cpus/cpu_arm_instr_loadstore.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (14 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 12138 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_arm_instr_loadstore.c,v 1.8 2005/10/05 21:17:32 debug Exp $
29 *
30 *
31 * TODO: Many things...
32 *
33 * o) Big-endian ARM loads/stores.
34 *
35 * o) Alignment checks!
36 *
37 * o) Native load/store if the endianness is the same as the host's
38 *
39 * o) "Base Updated Abort Model", which updates the base register
40 * even if the memory access failed.
41 *
42 * o) Some ARM implementations use pc+8, some use pc+12 for stores?
43 *
44 * o) All load/store variants with the PC register are not really
45 * valid. (E.g. a byte load into the PC register. What should that
46 * accomplish?)
47 *
48 * o) Perhaps an optimization for the case when offset = 0, because
49 * that's quite common, and also when the Reg expression is just
50 * a simple, non-rotated register (0..14).
51 */
52
53
54 /*
55 * General load/store, by using memory_rw(). If at all possible, memory_rw()
56 * then inserts the page into the translation array, so that the fast
57 * load/store routine below can be used for further accesses.
58 */
59 void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic)
60 {
61 #if !defined(A__P) && defined(A__W)
62 const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
63 #else
64 const int memory_rw_flags = CACHE_DATA;
65 #endif
66 #ifdef A__B
67 unsigned char data[1];
68 #else
69 #ifdef A__H
70 unsigned char data[2];
71 #else
72 unsigned char data[4];
73 #endif
74 #endif
75 uint32_t addr, low_pc, offset =
76 #ifndef A__U
77 -
78 #endif
79 #ifdef A__REG
80 R(cpu, ic, ic->arg[1], 0)
81 #else
82 ic->arg[1]
83 #endif
84 ;
85
86 low_pc = ((size_t)ic - (size_t)cpu->cd.arm.
87 cur_ic_page) / sizeof(struct arm_instr_call);
88 cpu->cd.arm.r[ARM_PC] &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
89 << ARM_INSTR_ALIGNMENT_SHIFT);
90 cpu->cd.arm.r[ARM_PC] += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
91 cpu->pc = cpu->cd.arm.r[ARM_PC];
92
93 addr = reg(ic->arg[0])
94 #ifdef A__P
95 + offset
96 #endif
97 ;
98
99 #ifdef A__L
100 /* Load: */
101 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
102 MEM_READ, memory_rw_flags)) {
103 /* load failed, an exception was generated */
104 return;
105 }
106 #ifdef A__B
107 reg(ic->arg[2]) =
108 #ifdef A__SIGNED
109 (int32_t)(int8_t)
110 #endif
111 data[0];
112 #else
113 #ifdef A__H
114 reg(ic->arg[2]) =
115 #ifdef A__SIGNED
116 (int32_t)(int16_t)
117 #endif
118 (data[0] + (data[1] << 8));
119 #else
120 reg(ic->arg[2]) = data[0] + (data[1] << 8) +
121 (data[2] << 16) + (data[3] << 24);
122 #endif
123 #endif
124 #else
125 /* Store: */
126 #ifdef A__B
127 data[0] = reg(ic->arg[2]);
128 #else
129 #ifdef A__H
130 data[0] = reg(ic->arg[2]);
131 data[1] = reg(ic->arg[2]) >> 8;
132 #else
133 data[0] = reg(ic->arg[2]);
134 data[1] = reg(ic->arg[2]) >> 8;
135 data[2] = reg(ic->arg[2]) >> 16;
136 data[3] = reg(ic->arg[2]) >> 24;
137 #endif
138 #endif
139 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
140 MEM_WRITE, memory_rw_flags)) {
141 /* store failed, an exception was generated */
142 return;
143 }
144 #endif
145
146 #ifdef A__P
147 #ifdef A__W
148 reg(ic->arg[0]) = addr;
149 #endif
150 #else /* post-index writeback */
151 reg(ic->arg[0]) = addr + offset;
152 #endif
153 }
154
155
156 /*
157 * Fast load/store, if the page is in the translation array.
158 */
159 void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
160 {
161 #if !defined(A__P) && defined(A__W)
162 /* T-bit: userland access. Use the general routine for that. */
163 A__NAME__general(cpu, ic);
164 #else
165 uint32_t offset =
166 #ifndef A__U
167 -
168 #endif
169 #ifdef A__REG
170 R(cpu, ic, ic->arg[1], 0)
171 #else
172 ic->arg[1]
173 #endif
174 ;
175 uint32_t addr = reg(ic->arg[0])
176 #ifdef A__P
177 + offset
178 #endif
179 ;
180 unsigned char *page = cpu->cd.arm.
181 #ifdef A__L
182 host_load
183 #else
184 host_store
185 #endif
186 [addr >> 12];
187
188 if (page == NULL) {
189 A__NAME__general(cpu, ic);
190 } else {
191 #ifdef A__L
192 #ifdef A__B
193 reg(ic->arg[2]) =
194 #ifdef A__SIGNED
195 (int32_t)(int8_t)
196 #endif
197 page[addr & 0xfff];
198 #else
199 #ifdef A__H
200 reg(ic->arg[2]) =
201 #ifdef A__SIGNED
202 (int32_t)(int16_t)
203 #endif
204 (page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8));
205 #else
206 reg(ic->arg[2]) = page[addr & 0xfff] +
207 (page[(addr & 0xfff) + 1] << 8) +
208 (page[(addr & 0xfff) + 2] << 16) +
209 (page[(addr & 0xfff) + 3] << 24);
210 #endif
211 #endif
212 #else
213 #ifdef A__B
214 page[addr & 0xfff] = reg(ic->arg[2]);
215 #else
216 #ifdef A__H
217 page[addr & 0xfff] = reg(ic->arg[2]);
218 page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
219 #else
220 page[addr & 0xfff] = reg(ic->arg[2]);
221 page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
222 page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16;
223 page[(addr & 0xfff)+3] = reg(ic->arg[2]) >> 24;
224 #endif
225 #endif
226 #endif
227
228 /* Index Write-back: */
229 #ifdef A__P
230 #ifdef A__W
231 reg(ic->arg[0]) = addr;
232 #endif
233 #else
234 /* post-index writeback */
235 reg(ic->arg[0]) = addr + offset;
236 #endif
237 }
238 #endif /* not T-bit */
239 }
240
241
242 /*
243 * Special case when loading or storing the ARM's PC register, or when the PC
244 * register is used as the base address register.
245 *
246 * o) Loads into the PC register cause a branch. If an exception occured
247 * during the load, then the PC register should already point to the
248 * exception handler, in which case we simply recalculate the pointers a
249 * second time (no harm is done by doing that).
250 *
251 * TODO: A tiny performance optimization would be to separate the two
252 * cases: a load where arg[0] = PC, and the case where arg[2] = PC.
253 *
254 * o) Stores store "PC of the current instruction + 12". The solution I have
255 * choosen is to calculate this value and place it into a temporary
256 * variable (tmp_pc), which is then used for the store.
257 */
258 void A__NAME_PC(struct cpu *cpu, struct arm_instr_call *ic)
259 {
260 #ifdef A__L
261 /* Load: */
262 if (ic->arg[0] == (size_t)(&cpu->cd.arm.tmp_pc)) {
263 /* tmp_pc = current PC + 8: */
264 uint32_t low_pc, tmp;
265 low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
266 sizeof(struct arm_instr_call);
267 tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
268 ARM_INSTR_ALIGNMENT_SHIFT);
269 tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
270 cpu->cd.arm.tmp_pc = tmp + 8;
271 }
272 A__NAME(cpu, ic);
273 if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) {
274 cpu->pc = cpu->cd.arm.r[ARM_PC];
275 arm_pc_to_pointers(cpu);
276 }
277 #else
278 /* Store: */
279 uint32_t low_pc, tmp;
280 /* Calculate tmp from this instruction's PC + 12 */
281 low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
282 sizeof(struct arm_instr_call);
283 tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
284 ARM_INSTR_ALIGNMENT_SHIFT);
285 tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
286 cpu->cd.arm.tmp_pc = tmp + 12;
287 A__NAME(cpu, ic);
288 #endif
289 }
290
291
292 #ifndef A__NOCONDITIONS
293 /* Load/stores with all registers except the PC register: */
294 void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
295 { if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME(cpu, ic); }
296 void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
297 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); }
298 void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
299 { if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME(cpu, ic); }
300 void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
301 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); }
302 void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
303 { if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME(cpu, ic); }
304 void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
305 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME(cpu, ic); }
306 void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
307 { if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME(cpu, ic); }
308 void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
309 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME(cpu, ic); }
310
311 void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
312 { if (cpu->cd.arm.cpsr & ARM_FLAG_C &&
313 !(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); }
314 void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
315 { if (cpu->cd.arm.cpsr & ARM_FLAG_Z ||
316 !(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); }
317 void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
318 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) ==
319 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); }
320 void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
321 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) !=
322 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); }
323 void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
324 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) ==
325 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) &&
326 !(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); }
327 void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
328 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) !=
329 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) ||
330 (cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); }
331
332
333 /* Load/stores with the PC register: */
334 void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic)
335 { if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME_PC(cpu, ic); }
336 void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic)
337 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); }
338 void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic)
339 { if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME_PC(cpu, ic); }
340 void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic)
341 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); }
342 void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic)
343 { if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME_PC(cpu, ic); }
344 void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic)
345 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME_PC(cpu, ic); }
346 void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic)
347 { if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME_PC(cpu, ic); }
348 void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic)
349 { if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME_PC(cpu, ic); }
350
351 void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic)
352 { if (cpu->cd.arm.cpsr & ARM_FLAG_C &&
353 !(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); }
354 void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic)
355 { if (cpu->cd.arm.cpsr & ARM_FLAG_Z ||
356 !(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); }
357 void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic)
358 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) ==
359 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); }
360 void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic)
361 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) !=
362 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); }
363 void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic)
364 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) ==
365 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) &&
366 !(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); }
367 void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic)
368 { if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) !=
369 ((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) ||
370 (cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); }
371 #endif

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