25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm_instr_loadstore.c,v 1.8 2005/10/05 21:17:32 debug Exp $ |
* $Id: cpu_arm_instr_loadstore.c,v 1.19 2005/11/19 18:53:07 debug Exp $ |
29 |
* |
* |
30 |
* |
* |
31 |
* TODO: Many things... |
* TODO: Many things... |
35 |
* o) Alignment checks! |
* o) Alignment checks! |
36 |
* |
* |
37 |
* o) Native load/store if the endianness is the same as the host's |
* o) Native load/store if the endianness is the same as the host's |
38 |
|
* (only implemented for little endian, so far, and it assumes that |
39 |
|
* alignment is correct!) |
40 |
* |
* |
41 |
* o) "Base Updated Abort Model", which updates the base register |
* o) "Base Updated Abort Model", which updates the base register |
42 |
* even if the memory access failed. |
* even if the memory access failed. |
53 |
*/ |
*/ |
54 |
|
|
55 |
|
|
56 |
|
#if defined(A__SIGNED) && defined(A__H) && !defined(A__L) |
57 |
|
#define A__STRD |
58 |
|
#endif |
59 |
|
|
60 |
|
|
61 |
/* |
/* |
62 |
* General load/store, by using memory_rw(). If at all possible, memory_rw() |
* General load/store, by using memory_rw(). If at all possible, memory_rw() |
63 |
* then inserts the page into the translation array, so that the fast |
* then inserts the page into the translation array, so that the fast |
70 |
#else |
#else |
71 |
const int memory_rw_flags = CACHE_DATA; |
const int memory_rw_flags = CACHE_DATA; |
72 |
#endif |
#endif |
73 |
|
|
74 |
|
#ifdef A__REG |
75 |
|
uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *) |
76 |
|
= (void *)(size_t)ic->arg[1]; |
77 |
|
#endif |
78 |
|
|
79 |
|
#ifdef A__STRD |
80 |
|
unsigned char data[8]; |
81 |
|
const int datalen = 8; |
82 |
|
#else |
83 |
#ifdef A__B |
#ifdef A__B |
84 |
unsigned char data[1]; |
unsigned char data[1]; |
85 |
|
const int datalen = 1; |
86 |
#else |
#else |
87 |
#ifdef A__H |
#ifdef A__H |
88 |
unsigned char data[2]; |
unsigned char data[2]; |
89 |
|
const int datalen = 2; |
90 |
|
#else |
91 |
|
const int datalen = 4; |
92 |
|
#ifdef HOST_LITTLE_ENDIAN |
93 |
|
unsigned char *data = (unsigned char *) ic->arg[2]; |
94 |
#else |
#else |
95 |
unsigned char data[4]; |
unsigned char data[4]; |
96 |
#endif |
#endif |
97 |
#endif |
#endif |
98 |
|
#endif |
99 |
|
#endif |
100 |
|
|
101 |
uint32_t addr, low_pc, offset = |
uint32_t addr, low_pc, offset = |
102 |
#ifndef A__U |
#ifndef A__U |
103 |
- |
- |
104 |
#endif |
#endif |
105 |
#ifdef A__REG |
#ifdef A__REG |
106 |
R(cpu, ic, ic->arg[1], 0) |
reg_func(cpu, ic); |
107 |
#else |
#else |
108 |
ic->arg[1] |
ic->arg[1]; |
109 |
#endif |
#endif |
|
; |
|
110 |
|
|
111 |
low_pc = ((size_t)ic - (size_t)cpu->cd.arm. |
low_pc = ((size_t)ic - (size_t)cpu->cd.arm. |
112 |
cur_ic_page) / sizeof(struct arm_instr_call); |
cur_ic_page) / sizeof(struct arm_instr_call); |
113 |
cpu->cd.arm.r[ARM_PC] &= ~((ARM_IC_ENTRIES_PER_PAGE-1) |
cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) |
114 |
<< ARM_INSTR_ALIGNMENT_SHIFT); |
<< ARM_INSTR_ALIGNMENT_SHIFT); |
115 |
cpu->cd.arm.r[ARM_PC] += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
|
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
|
116 |
|
|
117 |
addr = reg(ic->arg[0]) |
addr = reg(ic->arg[0]) |
118 |
#ifdef A__P |
#ifdef A__P |
122 |
|
|
123 |
#ifdef A__L |
#ifdef A__L |
124 |
/* Load: */ |
/* Load: */ |
125 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen, |
126 |
MEM_READ, memory_rw_flags)) { |
MEM_READ, memory_rw_flags)) { |
127 |
/* load failed, an exception was generated */ |
/* load failed, an exception was generated */ |
128 |
return; |
return; |
141 |
#endif |
#endif |
142 |
(data[0] + (data[1] << 8)); |
(data[0] + (data[1] << 8)); |
143 |
#else |
#else |
144 |
|
#ifdef HOST_LITTLE_ENDIAN |
145 |
|
/* Nothing. */ |
146 |
|
#else |
147 |
reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
148 |
(data[2] << 16) + (data[3] << 24); |
(data[2] << 16) + (data[3] << 24); |
149 |
#endif |
#endif |
150 |
#endif |
#endif |
151 |
|
#endif |
152 |
#else |
#else |
153 |
/* Store: */ |
/* Store: */ |
154 |
#ifdef A__B |
#if !defined(A__B) && !defined(A__H) && defined(HOST_LITTLE_ENDIAN) |
155 |
data[0] = reg(ic->arg[2]); |
#ifdef A__STRD |
156 |
|
*(uint32_t *)data = reg(ic->arg[2]); |
157 |
|
*(uint32_t *)(data + 4) = reg(ic->arg[2] + 4); |
158 |
|
#endif |
159 |
#else |
#else |
|
#ifdef A__H |
|
160 |
data[0] = reg(ic->arg[2]); |
data[0] = reg(ic->arg[2]); |
161 |
|
#ifndef A__B |
162 |
data[1] = reg(ic->arg[2]) >> 8; |
data[1] = reg(ic->arg[2]) >> 8; |
163 |
#else |
#if !defined(A__H) || defined(A__STRD) |
|
data[0] = reg(ic->arg[2]); |
|
164 |
data[1] = reg(ic->arg[2]) >> 8; |
data[1] = reg(ic->arg[2]) >> 8; |
165 |
data[2] = reg(ic->arg[2]) >> 16; |
data[2] = reg(ic->arg[2]) >> 16; |
166 |
data[3] = reg(ic->arg[2]) >> 24; |
data[3] = reg(ic->arg[2]) >> 24; |
167 |
|
#ifdef A__STRD |
168 |
|
data[4] = reg(ic->arg[2] + 4); |
169 |
|
data[5] = reg(ic->arg[2] + 4) >> 8; |
170 |
|
data[6] = reg(ic->arg[2] + 4) >> 16; |
171 |
|
data[7] = reg(ic->arg[2] + 4) >> 24; |
172 |
|
#endif |
173 |
|
#endif |
174 |
#endif |
#endif |
175 |
#endif |
#endif |
176 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen, |
177 |
MEM_WRITE, memory_rw_flags)) { |
MEM_WRITE, memory_rw_flags)) { |
178 |
/* store failed, an exception was generated */ |
/* store failed, an exception was generated */ |
179 |
return; |
return; |
195 |
*/ |
*/ |
196 |
void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
197 |
{ |
{ |
198 |
#if !defined(A__P) && defined(A__W) |
#ifdef A__STRD |
199 |
/* T-bit: userland access. Use the general routine for that. */ |
/* Chicken out, let's do this unoptimized for now: */ |
200 |
A__NAME__general(cpu, ic); |
A__NAME__general(cpu, ic); |
201 |
#else |
#else |
202 |
|
#ifdef A__REG |
203 |
|
uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *) |
204 |
|
= (void *)(size_t)ic->arg[1]; |
205 |
|
#endif |
206 |
uint32_t offset = |
uint32_t offset = |
207 |
#ifndef A__U |
#ifndef A__U |
208 |
- |
- |
209 |
#endif |
#endif |
210 |
#ifdef A__REG |
#ifdef A__REG |
211 |
R(cpu, ic, ic->arg[1], 0) |
reg_func(cpu, ic); |
212 |
#else |
#else |
213 |
ic->arg[1] |
ic->arg[1]; |
214 |
#endif |
#endif |
|
; |
|
215 |
uint32_t addr = reg(ic->arg[0]) |
uint32_t addr = reg(ic->arg[0]) |
216 |
#ifdef A__P |
#ifdef A__P |
217 |
+ offset |
+ offset |
225 |
#endif |
#endif |
226 |
[addr >> 12]; |
[addr >> 12]; |
227 |
|
|
228 |
|
|
229 |
|
#if !defined(A__P) && defined(A__W) |
230 |
|
/* |
231 |
|
* T-bit: userland access: check the corresponding bit in the |
232 |
|
* is_userpage array. If it is set, then we're ok. Otherwise: use the |
233 |
|
* generic function. |
234 |
|
*/ |
235 |
|
uint32_t x = cpu->cd.arm.is_userpage[addr >> 17]; |
236 |
|
if (!(x & (1 << ((addr >> 12) & 31)))) |
237 |
|
A__NAME__general(cpu, ic); |
238 |
|
else |
239 |
|
#endif |
240 |
|
|
241 |
|
|
242 |
if (page == NULL) { |
if (page == NULL) { |
243 |
A__NAME__general(cpu, ic); |
A__NAME__general(cpu, ic); |
244 |
} else { |
} else { |
245 |
#ifdef A__L |
#ifdef A__L |
246 |
#ifdef A__B |
#ifdef A__B |
257 |
#endif |
#endif |
258 |
(page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8)); |
(page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8)); |
259 |
#else |
#else |
260 |
|
#ifdef HOST_LITTLE_ENDIAN |
261 |
|
reg(ic->arg[2]) = *(uint32_t *)(page + (addr & 0xffc)); |
262 |
|
#else |
263 |
reg(ic->arg[2]) = page[addr & 0xfff] + |
reg(ic->arg[2]) = page[addr & 0xfff] + |
264 |
(page[(addr & 0xfff) + 1] << 8) + |
(page[(addr & 0xfff) + 1] << 8) + |
265 |
(page[(addr & 0xfff) + 2] << 16) + |
(page[(addr & 0xfff) + 2] << 16) + |
266 |
(page[(addr & 0xfff) + 3] << 24); |
(page[(addr & 0xfff) + 3] << 24); |
267 |
#endif |
#endif |
268 |
#endif |
#endif |
269 |
|
#endif |
270 |
#else |
#else |
271 |
#ifdef A__B |
#ifdef A__B |
272 |
page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
275 |
page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
276 |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
277 |
#else |
#else |
278 |
|
#ifdef HOST_LITTLE_ENDIAN |
279 |
|
*(uint32_t *)(page + (addr & 0xffc)) = reg(ic->arg[2]); |
280 |
|
#else |
281 |
page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
282 |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
283 |
page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16; |
page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16; |
285 |
#endif |
#endif |
286 |
#endif |
#endif |
287 |
#endif |
#endif |
288 |
|
#endif |
289 |
|
|
290 |
/* Index Write-back: */ |
/* Index Write-back: */ |
291 |
#ifdef A__P |
#ifdef A__P |
297 |
reg(ic->arg[0]) = addr + offset; |
reg(ic->arg[0]) = addr + offset; |
298 |
#endif |
#endif |
299 |
} |
} |
300 |
#endif /* not T-bit */ |
#endif /* not STRD */ |
301 |
} |
} |
302 |
|
|
303 |
|
|
326 |
uint32_t low_pc, tmp; |
uint32_t low_pc, tmp; |
327 |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
328 |
sizeof(struct arm_instr_call); |
sizeof(struct arm_instr_call); |
329 |
tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
330 |
ARM_INSTR_ALIGNMENT_SHIFT); |
ARM_INSTR_ALIGNMENT_SHIFT); |
331 |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
332 |
cpu->cd.arm.tmp_pc = tmp + 8; |
cpu->cd.arm.tmp_pc = tmp + 8; |
334 |
A__NAME(cpu, ic); |
A__NAME(cpu, ic); |
335 |
if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) { |
if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) { |
336 |
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
337 |
arm_pc_to_pointers(cpu); |
quick_pc_to_pointers(cpu); |
338 |
|
if (cpu->machine->show_trace_tree) |
339 |
|
cpu_functioncall_trace(cpu, cpu->pc); |
340 |
} |
} |
341 |
#else |
#else |
342 |
/* Store: */ |
/* Store: */ |
344 |
/* Calculate tmp from this instruction's PC + 12 */ |
/* Calculate tmp from this instruction's PC + 12 */ |
345 |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
346 |
sizeof(struct arm_instr_call); |
sizeof(struct arm_instr_call); |
347 |
tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
348 |
ARM_INSTR_ALIGNMENT_SHIFT); |
ARM_INSTR_ALIGNMENT_SHIFT); |
349 |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
350 |
cpu->cd.arm.tmp_pc = tmp + 12; |
cpu->cd.arm.tmp_pc = tmp + 12; |
356 |
#ifndef A__NOCONDITIONS |
#ifndef A__NOCONDITIONS |
357 |
/* Load/stores with all registers except the PC register: */ |
/* Load/stores with all registers except the PC register: */ |
358 |
void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
359 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); } |
360 |
void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
361 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
362 |
void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
363 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); } |
364 |
void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
365 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); } |
366 |
void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
367 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); } |
368 |
void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
369 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); } |
370 |
void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
371 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); } |
372 |
void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
373 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); } |
374 |
|
|
375 |
void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
376 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
{ if (cpu->cd.arm.flags & ARM_F_C && |
377 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
378 |
void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
379 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
{ if (cpu->cd.arm.flags & ARM_F_Z || |
380 |
!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); } |
381 |
void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
382 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
383 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); } |
384 |
void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
385 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
386 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); } |
387 |
void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
388 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
389 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
((cpu->cd.arm.flags & ARM_F_V)?1:0) && |
390 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
391 |
void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
392 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
393 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
((cpu->cd.arm.flags & ARM_F_V)?1:0) || |
394 |
(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
395 |
|
|
396 |
|
|
397 |
/* Load/stores with the PC register: */ |
/* Load/stores with the PC register: */ |
398 |
void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic) |
399 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME_PC(cpu, ic); } |
400 |
void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic) |
401 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
402 |
void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic) |
403 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME_PC(cpu, ic); } |
404 |
void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic) |
405 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); } |
406 |
void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic) |
407 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME_PC(cpu, ic); } |
408 |
void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic) |
409 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME_PC(cpu, ic); } |
410 |
void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic) |
411 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME_PC(cpu, ic); } |
412 |
void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic) |
413 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME_PC(cpu, ic); } |
414 |
|
|
415 |
void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic) |
416 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
{ if (cpu->cd.arm.flags & ARM_F_C && |
417 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
418 |
void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic) |
419 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
{ if (cpu->cd.arm.flags & ARM_F_Z || |
420 |
!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); } |
421 |
void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic) |
422 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
423 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); } |
424 |
void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic) |
425 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
426 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); } |
427 |
void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic) |
428 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
429 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
((cpu->cd.arm.flags & ARM_F_V)?1:0) && |
430 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
431 |
void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic) |
432 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
433 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
((cpu->cd.arm.flags & ARM_F_V)?1:0) || |
434 |
(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
435 |
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#endif |
436 |
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437 |
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438 |
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#ifdef A__STRD |
439 |
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#undef A__STRD |
440 |
#endif |
#endif |