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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm_instr_loadstore.c,v 1.9 2005/10/09 21:32:07 debug Exp $ |
* $Id: cpu_arm_instr_loadstore.c,v 1.20 2006/02/16 19:49:04 debug Exp $ |
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* |
* |
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* |
* |
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* TODO: Many things... |
* TODO: Many things... |
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* o) Alignment checks! |
* o) Alignment checks! |
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* |
* |
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* o) Native load/store if the endianness is the same as the host's |
* o) Native load/store if the endianness is the same as the host's |
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* (only implemented for little endian, so far, and it assumes that |
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* alignment is correct!) |
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* |
* |
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* o) "Base Updated Abort Model", which updates the base register |
* o) "Base Updated Abort Model", which updates the base register |
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* even if the memory access failed. |
* even if the memory access failed. |
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*/ |
*/ |
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#if defined(A__SIGNED) && !defined(A__H) && !defined(A__L) |
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#define A__LDRD |
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#endif |
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#if defined(A__SIGNED) && defined(A__H) && !defined(A__L) |
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#define A__STRD |
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#endif |
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/* |
/* |
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* General load/store, by using memory_rw(). If at all possible, memory_rw() |
* General load/store, by using memory_rw(). If at all possible, memory_rw() |
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* then inserts the page into the translation array, so that the fast |
* then inserts the page into the translation array, so that the fast |
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#else |
#else |
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const int memory_rw_flags = CACHE_DATA; |
const int memory_rw_flags = CACHE_DATA; |
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#endif |
#endif |
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#ifdef A__REG |
#ifdef A__REG |
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uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *) |
uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *) |
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= (void *)(size_t)ic->arg[1]; |
= (void *)(size_t)ic->arg[1]; |
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#endif |
#endif |
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#if defined(A__STRD) || defined(A__LDRD) |
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unsigned char data[8]; |
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const int datalen = 8; |
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#else |
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#ifdef A__B |
#ifdef A__B |
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unsigned char data[1]; |
unsigned char data[1]; |
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const int datalen = 1; |
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#else |
#else |
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#ifdef A__H |
#ifdef A__H |
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unsigned char data[2]; |
unsigned char data[2]; |
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const int datalen = 2; |
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#else |
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const int datalen = 4; |
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#ifdef HOST_LITTLE_ENDIAN |
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unsigned char *data = (unsigned char *) ic->arg[2]; |
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#else |
#else |
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unsigned char data[4]; |
unsigned char data[4]; |
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#endif |
#endif |
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#endif |
#endif |
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#endif |
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#endif |
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uint32_t addr, low_pc, offset = |
uint32_t addr, low_pc, offset = |
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#ifndef A__U |
#ifndef A__U |
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- |
- |
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low_pc = ((size_t)ic - (size_t)cpu->cd.arm. |
low_pc = ((size_t)ic - (size_t)cpu->cd.arm. |
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cur_ic_page) / sizeof(struct arm_instr_call); |
cur_ic_page) / sizeof(struct arm_instr_call); |
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cpu->cd.arm.r[ARM_PC] &= ~((ARM_IC_ENTRIES_PER_PAGE-1) |
cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) |
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<< ARM_INSTR_ALIGNMENT_SHIFT); |
<< ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->cd.arm.r[ARM_PC] += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc = cpu->cd.arm.r[ARM_PC]; |
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addr = reg(ic->arg[0]) |
addr = reg(ic->arg[0]) |
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#ifdef A__P |
#ifdef A__P |
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#endif |
#endif |
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; |
; |
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#ifdef A__L |
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#if defined(A__L) || defined(A__LDRD) |
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/* Load: */ |
/* Load: */ |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen, |
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MEM_READ, memory_rw_flags)) { |
MEM_READ, memory_rw_flags)) { |
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/* load failed, an exception was generated */ |
/* load failed, an exception was generated */ |
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return; |
return; |
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} |
} |
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#ifdef A__B |
#if defined(A__B) && !defined(A__LDRD) |
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reg(ic->arg[2]) = |
reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
#ifdef A__SIGNED |
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(int32_t)(int8_t) |
(int32_t)(int8_t) |
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#endif |
#endif |
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data[0]; |
data[0]; |
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#else |
#else |
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#ifdef A__H |
#if defined(A__H) && !defined(A__LDRD) |
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reg(ic->arg[2]) = |
reg(ic->arg[2]) = |
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#ifdef A__SIGNED |
#ifdef A__SIGNED |
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(int32_t)(int16_t) |
(int32_t)(int16_t) |
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#endif |
#endif |
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(data[0] + (data[1] << 8)); |
(data[0] + (data[1] << 8)); |
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#else |
#else |
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#ifndef A__LDRD |
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#ifdef HOST_LITTLE_ENDIAN |
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/* Nothing. */ |
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#else |
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reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
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(data[2] << 16) + (data[3] << 24); |
(data[2] << 16) + (data[3] << 24); |
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#endif |
#endif |
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#else |
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reg(ic->arg[2]) = data[0] + (data[1] << 8) + |
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(data[2] << 16) + (data[3] << 24); |
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reg(((uint32_t *)ic->arg[2]) + 1) = data[4] + (data[5] << 8) + |
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(data[6] << 16) + (data[7] << 24); |
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#endif |
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#endif |
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#endif |
#endif |
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#else |
#else |
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/* Store: */ |
/* Store: */ |
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#ifdef A__B |
#if !defined(A__B) && !defined(A__H) && defined(HOST_LITTLE_ENDIAN) |
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data[0] = reg(ic->arg[2]); |
#ifdef A__STRD |
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*(uint32_t *)data = reg(ic->arg[2]); |
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*(uint32_t *)(data + 4) = reg(ic->arg[2] + 4); |
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#endif |
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#else |
#else |
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#ifdef A__H |
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data[0] = reg(ic->arg[2]); |
data[0] = reg(ic->arg[2]); |
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#ifndef A__B |
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data[1] = reg(ic->arg[2]) >> 8; |
data[1] = reg(ic->arg[2]) >> 8; |
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#else |
#if !defined(A__H) || defined(A__STRD) |
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data[0] = reg(ic->arg[2]); |
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data[1] = reg(ic->arg[2]) >> 8; |
data[1] = reg(ic->arg[2]) >> 8; |
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data[2] = reg(ic->arg[2]) >> 16; |
data[2] = reg(ic->arg[2]) >> 16; |
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data[3] = reg(ic->arg[2]) >> 24; |
data[3] = reg(ic->arg[2]) >> 24; |
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#ifdef A__STRD |
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data[4] = reg(ic->arg[2] + 4); |
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data[5] = reg(ic->arg[2] + 4) >> 8; |
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data[6] = reg(ic->arg[2] + 4) >> 16; |
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data[7] = reg(ic->arg[2] + 4) >> 24; |
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#endif |
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#endif |
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#endif |
#endif |
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#endif |
#endif |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen, |
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MEM_WRITE, memory_rw_flags)) { |
MEM_WRITE, memory_rw_flags)) { |
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/* store failed, an exception was generated */ |
/* store failed, an exception was generated */ |
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return; |
return; |
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*/ |
*/ |
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void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME(struct cpu *cpu, struct arm_instr_call *ic) |
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{ |
{ |
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#if !defined(A__P) && defined(A__W) |
#if defined(A__LDRD) || defined(A__STRD) |
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/* T-bit: userland access. Use the general routine for that. */ |
/* Chicken out, let's do this unoptimized for now: */ |
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A__NAME__general(cpu, ic); |
A__NAME__general(cpu, ic); |
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#else |
#else |
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#ifdef A__REG |
#ifdef A__REG |
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#endif |
#endif |
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[addr >> 12]; |
[addr >> 12]; |
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#if !defined(A__P) && defined(A__W) |
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/* |
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* T-bit: userland access: check the corresponding bit in the |
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* is_userpage array. If it is set, then we're ok. Otherwise: use the |
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* generic function. |
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*/ |
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uint32_t x = cpu->cd.arm.is_userpage[addr >> 17]; |
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if (!(x & (1 << ((addr >> 12) & 31)))) |
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A__NAME__general(cpu, ic); |
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else |
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#endif |
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if (page == NULL) { |
if (page == NULL) { |
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A__NAME__general(cpu, ic); |
A__NAME__general(cpu, ic); |
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} else { |
} else { |
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#ifdef A__L |
#ifdef A__L |
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#ifdef A__B |
#ifdef A__B |
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#endif |
#endif |
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(page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8)); |
(page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8)); |
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#else |
#else |
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#ifdef HOST_LITTLE_ENDIAN |
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reg(ic->arg[2]) = *(uint32_t *)(page + (addr & 0xffc)); |
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#else |
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reg(ic->arg[2]) = page[addr & 0xfff] + |
reg(ic->arg[2]) = page[addr & 0xfff] + |
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(page[(addr & 0xfff) + 1] << 8) + |
(page[(addr & 0xfff) + 1] << 8) + |
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(page[(addr & 0xfff) + 2] << 16) + |
(page[(addr & 0xfff) + 2] << 16) + |
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(page[(addr & 0xfff) + 3] << 24); |
(page[(addr & 0xfff) + 3] << 24); |
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#endif |
#endif |
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#endif |
#endif |
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|
#endif |
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#else |
#else |
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#ifdef A__B |
#ifdef A__B |
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page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
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page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
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page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
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#else |
#else |
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#ifdef HOST_LITTLE_ENDIAN |
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*(uint32_t *)(page + (addr & 0xffc)) = reg(ic->arg[2]); |
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#else |
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page[addr & 0xfff] = reg(ic->arg[2]); |
page[addr & 0xfff] = reg(ic->arg[2]); |
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page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8; |
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page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16; |
page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16; |
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#endif |
#endif |
297 |
#endif |
#endif |
298 |
#endif |
#endif |
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#endif |
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/* Index Write-back: */ |
/* Index Write-back: */ |
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#ifdef A__P |
#ifdef A__P |
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reg(ic->arg[0]) = addr + offset; |
reg(ic->arg[0]) = addr + offset; |
309 |
#endif |
#endif |
310 |
} |
} |
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#endif /* not T-bit */ |
#endif /* not STRD */ |
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} |
} |
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uint32_t low_pc, tmp; |
uint32_t low_pc, tmp; |
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low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
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sizeof(struct arm_instr_call); |
sizeof(struct arm_instr_call); |
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tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
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ARM_INSTR_ALIGNMENT_SHIFT); |
ARM_INSTR_ALIGNMENT_SHIFT); |
342 |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
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cpu->cd.arm.tmp_pc = tmp + 8; |
cpu->cd.arm.tmp_pc = tmp + 8; |
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A__NAME(cpu, ic); |
A__NAME(cpu, ic); |
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if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) { |
if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) { |
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cpu->pc = cpu->cd.arm.r[ARM_PC]; |
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
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arm_pc_to_pointers(cpu); |
quick_pc_to_pointers(cpu); |
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if (cpu->machine->show_trace_tree) |
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cpu_functioncall_trace(cpu, cpu->pc); |
351 |
} |
} |
352 |
#else |
#else |
353 |
/* Store: */ |
/* Store: */ |
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/* Calculate tmp from this instruction's PC + 12 */ |
/* Calculate tmp from this instruction's PC + 12 */ |
356 |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) / |
357 |
sizeof(struct arm_instr_call); |
sizeof(struct arm_instr_call); |
358 |
tmp = cpu->cd.arm.r[ARM_PC] & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) << |
359 |
ARM_INSTR_ALIGNMENT_SHIFT); |
ARM_INSTR_ALIGNMENT_SHIFT); |
360 |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT); |
361 |
cpu->cd.arm.tmp_pc = tmp + 12; |
cpu->cd.arm.tmp_pc = tmp + 12; |
367 |
#ifndef A__NOCONDITIONS |
#ifndef A__NOCONDITIONS |
368 |
/* Load/stores with all registers except the PC register: */ |
/* Load/stores with all registers except the PC register: */ |
369 |
void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic) |
370 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); } |
371 |
void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic) |
372 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
373 |
void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic) |
374 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); } |
375 |
void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic) |
376 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); } |
377 |
void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic) |
378 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); } |
379 |
void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic) |
380 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); } |
381 |
void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic) |
382 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); } |
383 |
void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic) |
384 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); } |
385 |
|
|
386 |
void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic) |
387 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
{ if (cpu->cd.arm.flags & ARM_F_C && |
388 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
389 |
void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic) |
390 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
{ if (cpu->cd.arm.flags & ARM_F_Z || |
391 |
!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); } |
392 |
void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic) |
393 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
394 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); } |
395 |
void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic) |
396 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
397 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); } |
398 |
void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic) |
399 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
400 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
((cpu->cd.arm.flags & ARM_F_V)?1:0) && |
401 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
402 |
void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic) |
403 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
404 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
((cpu->cd.arm.flags & ARM_F_V)?1:0) || |
405 |
(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME(cpu, ic); } |
(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); } |
406 |
|
|
407 |
|
|
408 |
/* Load/stores with the PC register: */ |
/* Load/stores with the PC register: */ |
409 |
void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic) |
410 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_Z) A__NAME_PC(cpu, ic); } |
411 |
void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic) |
412 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
413 |
void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic) |
414 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_C) A__NAME_PC(cpu, ic); } |
415 |
void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic) |
416 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); } |
417 |
void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic) |
418 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_N) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_N) A__NAME_PC(cpu, ic); } |
419 |
void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic) |
420 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_N)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME_PC(cpu, ic); } |
421 |
void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic) |
422 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_V) A__NAME_PC(cpu, ic); } |
{ if (cpu->cd.arm.flags & ARM_F_V) A__NAME_PC(cpu, ic); } |
423 |
void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic) |
424 |
{ if (!(cpu->cd.arm.cpsr & ARM_FLAG_V)) A__NAME_PC(cpu, ic); } |
{ if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME_PC(cpu, ic); } |
425 |
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|
426 |
void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic) |
427 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_C && |
{ if (cpu->cd.arm.flags & ARM_F_C && |
428 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
429 |
void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic) |
430 |
{ if (cpu->cd.arm.cpsr & ARM_FLAG_Z || |
{ if (cpu->cd.arm.flags & ARM_F_Z || |
431 |
!(cpu->cd.arm.cpsr & ARM_FLAG_C)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); } |
432 |
void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic) |
433 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
434 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); } |
435 |
void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic) |
436 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
437 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0)) A__NAME_PC(cpu, ic); } |
((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); } |
438 |
void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic) |
439 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) == |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) == |
440 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) && |
((cpu->cd.arm.flags & ARM_F_V)?1:0) && |
441 |
!(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
442 |
void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic) |
void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic) |
443 |
{ if (((cpu->cd.arm.cpsr & ARM_FLAG_N)?1:0) != |
{ if (((cpu->cd.arm.flags & ARM_F_N)?1:0) != |
444 |
((cpu->cd.arm.cpsr & ARM_FLAG_V)?1:0) || |
((cpu->cd.arm.flags & ARM_F_V)?1:0) || |
445 |
(cpu->cd.arm.cpsr & ARM_FLAG_Z)) A__NAME_PC(cpu, ic); } |
(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); } |
446 |
#endif |
#endif |
447 |
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448 |
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449 |
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#ifdef A__LDRD |
450 |
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#undef A__LDRD |
451 |
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#endif |
452 |
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453 |
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#ifdef A__STRD |
454 |
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#undef A__STRD |
455 |
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#endif |
456 |
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