/[gxemul]/trunk/src/cpus/cpu_arm_instr_loadstore.c
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Annotation of /trunk/src/cpus/cpu_arm_instr_loadstore.c

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Revision 20 - (hide annotations)
Mon Oct 8 16:19:23 2007 UTC (14 years, 3 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 20 * $Id: cpu_arm_instr_loadstore.c,v 1.19 2005/11/19 18:53:07 debug Exp $
29 dpavlin 14 *
30     *
31     * TODO: Many things...
32     *
33     * o) Big-endian ARM loads/stores.
34     *
35     * o) Alignment checks!
36     *
37     * o) Native load/store if the endianness is the same as the host's
38 dpavlin 18 * (only implemented for little endian, so far, and it assumes that
39     * alignment is correct!)
40 dpavlin 14 *
41     * o) "Base Updated Abort Model", which updates the base register
42     * even if the memory access failed.
43     *
44     * o) Some ARM implementations use pc+8, some use pc+12 for stores?
45     *
46     * o) All load/store variants with the PC register are not really
47     * valid. (E.g. a byte load into the PC register. What should that
48     * accomplish?)
49     *
50     * o) Perhaps an optimization for the case when offset = 0, because
51     * that's quite common, and also when the Reg expression is just
52     * a simple, non-rotated register (0..14).
53     */
54    
55    
56 dpavlin 18 #if defined(A__SIGNED) && defined(A__H) && !defined(A__L)
57     #define A__STRD
58     #endif
59    
60    
61 dpavlin 14 /*
62     * General load/store, by using memory_rw(). If at all possible, memory_rw()
63     * then inserts the page into the translation array, so that the fast
64     * load/store routine below can be used for further accesses.
65     */
66     void A__NAME__general(struct cpu *cpu, struct arm_instr_call *ic)
67     {
68     #if !defined(A__P) && defined(A__W)
69     const int memory_rw_flags = CACHE_DATA | MEMORY_USER_ACCESS;
70     #else
71     const int memory_rw_flags = CACHE_DATA;
72     #endif
73 dpavlin 18
74 dpavlin 16 #ifdef A__REG
75     uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
76     = (void *)(size_t)ic->arg[1];
77     #endif
78 dpavlin 18
79     #ifdef A__STRD
80     unsigned char data[8];
81     const int datalen = 8;
82     #else
83 dpavlin 14 #ifdef A__B
84     unsigned char data[1];
85 dpavlin 18 const int datalen = 1;
86 dpavlin 14 #else
87     #ifdef A__H
88     unsigned char data[2];
89 dpavlin 18 const int datalen = 2;
90 dpavlin 14 #else
91 dpavlin 18 const int datalen = 4;
92     #ifdef HOST_LITTLE_ENDIAN
93     unsigned char *data = (unsigned char *) ic->arg[2];
94     #else
95 dpavlin 14 unsigned char data[4];
96     #endif
97     #endif
98 dpavlin 18 #endif
99     #endif
100    
101 dpavlin 14 uint32_t addr, low_pc, offset =
102     #ifndef A__U
103     -
104     #endif
105     #ifdef A__REG
106 dpavlin 16 reg_func(cpu, ic);
107 dpavlin 14 #else
108 dpavlin 16 ic->arg[1];
109 dpavlin 14 #endif
110    
111     low_pc = ((size_t)ic - (size_t)cpu->cd.arm.
112     cur_ic_page) / sizeof(struct arm_instr_call);
113 dpavlin 20 cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1)
114 dpavlin 14 << ARM_INSTR_ALIGNMENT_SHIFT);
115 dpavlin 20 cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
116 dpavlin 14
117     addr = reg(ic->arg[0])
118     #ifdef A__P
119     + offset
120     #endif
121     ;
122    
123     #ifdef A__L
124     /* Load: */
125 dpavlin 18 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
126 dpavlin 14 MEM_READ, memory_rw_flags)) {
127     /* load failed, an exception was generated */
128     return;
129     }
130     #ifdef A__B
131     reg(ic->arg[2]) =
132     #ifdef A__SIGNED
133     (int32_t)(int8_t)
134     #endif
135     data[0];
136     #else
137     #ifdef A__H
138     reg(ic->arg[2]) =
139     #ifdef A__SIGNED
140     (int32_t)(int16_t)
141     #endif
142     (data[0] + (data[1] << 8));
143     #else
144 dpavlin 18 #ifdef HOST_LITTLE_ENDIAN
145     /* Nothing. */
146     #else
147 dpavlin 14 reg(ic->arg[2]) = data[0] + (data[1] << 8) +
148     (data[2] << 16) + (data[3] << 24);
149     #endif
150     #endif
151 dpavlin 18 #endif
152 dpavlin 14 #else
153     /* Store: */
154 dpavlin 18 #if !defined(A__B) && !defined(A__H) && defined(HOST_LITTLE_ENDIAN)
155     #ifdef A__STRD
156     *(uint32_t *)data = reg(ic->arg[2]);
157     *(uint32_t *)(data + 4) = reg(ic->arg[2] + 4);
158     #endif
159 dpavlin 14 #else
160     data[0] = reg(ic->arg[2]);
161 dpavlin 18 #ifndef A__B
162 dpavlin 14 data[1] = reg(ic->arg[2]) >> 8;
163 dpavlin 18 #if !defined(A__H) || defined(A__STRD)
164 dpavlin 14 data[1] = reg(ic->arg[2]) >> 8;
165     data[2] = reg(ic->arg[2]) >> 16;
166     data[3] = reg(ic->arg[2]) >> 24;
167 dpavlin 18 #ifdef A__STRD
168     data[4] = reg(ic->arg[2] + 4);
169     data[5] = reg(ic->arg[2] + 4) >> 8;
170     data[6] = reg(ic->arg[2] + 4) >> 16;
171     data[7] = reg(ic->arg[2] + 4) >> 24;
172 dpavlin 14 #endif
173     #endif
174 dpavlin 18 #endif
175     #endif
176     if (!cpu->memory_rw(cpu, cpu->mem, addr, data, datalen,
177 dpavlin 14 MEM_WRITE, memory_rw_flags)) {
178     /* store failed, an exception was generated */
179     return;
180     }
181     #endif
182    
183     #ifdef A__P
184     #ifdef A__W
185     reg(ic->arg[0]) = addr;
186     #endif
187     #else /* post-index writeback */
188     reg(ic->arg[0]) = addr + offset;
189     #endif
190     }
191    
192    
193     /*
194     * Fast load/store, if the page is in the translation array.
195     */
196     void A__NAME(struct cpu *cpu, struct arm_instr_call *ic)
197     {
198 dpavlin 18 #ifdef A__STRD
199     /* Chicken out, let's do this unoptimized for now: */
200 dpavlin 14 A__NAME__general(cpu, ic);
201     #else
202 dpavlin 16 #ifdef A__REG
203     uint32_t (*reg_func)(struct cpu *, struct arm_instr_call *)
204     = (void *)(size_t)ic->arg[1];
205     #endif
206 dpavlin 14 uint32_t offset =
207     #ifndef A__U
208     -
209     #endif
210     #ifdef A__REG
211 dpavlin 16 reg_func(cpu, ic);
212 dpavlin 14 #else
213 dpavlin 16 ic->arg[1];
214 dpavlin 14 #endif
215     uint32_t addr = reg(ic->arg[0])
216     #ifdef A__P
217     + offset
218     #endif
219     ;
220     unsigned char *page = cpu->cd.arm.
221     #ifdef A__L
222     host_load
223     #else
224     host_store
225     #endif
226     [addr >> 12];
227    
228 dpavlin 18
229     #if !defined(A__P) && defined(A__W)
230     /*
231     * T-bit: userland access: check the corresponding bit in the
232     * is_userpage array. If it is set, then we're ok. Otherwise: use the
233     * generic function.
234     */
235 dpavlin 20 uint32_t x = cpu->cd.arm.is_userpage[addr >> 17];
236     if (!(x & (1 << ((addr >> 12) & 31))))
237 dpavlin 18 A__NAME__general(cpu, ic);
238     else
239     #endif
240    
241    
242 dpavlin 14 if (page == NULL) {
243 dpavlin 18 A__NAME__general(cpu, ic);
244 dpavlin 14 } else {
245     #ifdef A__L
246     #ifdef A__B
247     reg(ic->arg[2]) =
248     #ifdef A__SIGNED
249     (int32_t)(int8_t)
250     #endif
251     page[addr & 0xfff];
252     #else
253     #ifdef A__H
254     reg(ic->arg[2]) =
255     #ifdef A__SIGNED
256     (int32_t)(int16_t)
257     #endif
258     (page[addr & 0xfff] + (page[(addr & 0xfff) + 1] << 8));
259     #else
260 dpavlin 18 #ifdef HOST_LITTLE_ENDIAN
261     reg(ic->arg[2]) = *(uint32_t *)(page + (addr & 0xffc));
262     #else
263 dpavlin 14 reg(ic->arg[2]) = page[addr & 0xfff] +
264     (page[(addr & 0xfff) + 1] << 8) +
265     (page[(addr & 0xfff) + 2] << 16) +
266     (page[(addr & 0xfff) + 3] << 24);
267     #endif
268     #endif
269 dpavlin 18 #endif
270 dpavlin 14 #else
271     #ifdef A__B
272     page[addr & 0xfff] = reg(ic->arg[2]);
273     #else
274     #ifdef A__H
275     page[addr & 0xfff] = reg(ic->arg[2]);
276     page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
277     #else
278 dpavlin 18 #ifdef HOST_LITTLE_ENDIAN
279     *(uint32_t *)(page + (addr & 0xffc)) = reg(ic->arg[2]);
280     #else
281 dpavlin 14 page[addr & 0xfff] = reg(ic->arg[2]);
282     page[(addr & 0xfff)+1] = reg(ic->arg[2]) >> 8;
283     page[(addr & 0xfff)+2] = reg(ic->arg[2]) >> 16;
284     page[(addr & 0xfff)+3] = reg(ic->arg[2]) >> 24;
285     #endif
286     #endif
287     #endif
288 dpavlin 18 #endif
289 dpavlin 14
290     /* Index Write-back: */
291     #ifdef A__P
292     #ifdef A__W
293     reg(ic->arg[0]) = addr;
294     #endif
295     #else
296     /* post-index writeback */
297     reg(ic->arg[0]) = addr + offset;
298     #endif
299     }
300 dpavlin 18 #endif /* not STRD */
301 dpavlin 14 }
302    
303    
304     /*
305     * Special case when loading or storing the ARM's PC register, or when the PC
306     * register is used as the base address register.
307     *
308     * o) Loads into the PC register cause a branch. If an exception occured
309     * during the load, then the PC register should already point to the
310     * exception handler, in which case we simply recalculate the pointers a
311     * second time (no harm is done by doing that).
312     *
313     * TODO: A tiny performance optimization would be to separate the two
314     * cases: a load where arg[0] = PC, and the case where arg[2] = PC.
315     *
316     * o) Stores store "PC of the current instruction + 12". The solution I have
317     * choosen is to calculate this value and place it into a temporary
318     * variable (tmp_pc), which is then used for the store.
319     */
320     void A__NAME_PC(struct cpu *cpu, struct arm_instr_call *ic)
321     {
322     #ifdef A__L
323     /* Load: */
324     if (ic->arg[0] == (size_t)(&cpu->cd.arm.tmp_pc)) {
325     /* tmp_pc = current PC + 8: */
326     uint32_t low_pc, tmp;
327     low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
328     sizeof(struct arm_instr_call);
329 dpavlin 20 tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
330 dpavlin 14 ARM_INSTR_ALIGNMENT_SHIFT);
331     tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
332     cpu->cd.arm.tmp_pc = tmp + 8;
333     }
334     A__NAME(cpu, ic);
335     if (ic->arg[2] == (size_t)(&cpu->cd.arm.r[ARM_PC])) {
336     cpu->pc = cpu->cd.arm.r[ARM_PC];
337 dpavlin 20 quick_pc_to_pointers(cpu);
338 dpavlin 18 if (cpu->machine->show_trace_tree)
339     cpu_functioncall_trace(cpu, cpu->pc);
340 dpavlin 14 }
341     #else
342     /* Store: */
343     uint32_t low_pc, tmp;
344     /* Calculate tmp from this instruction's PC + 12 */
345     low_pc = ((size_t)ic - (size_t) cpu->cd.arm.cur_ic_page) /
346     sizeof(struct arm_instr_call);
347 dpavlin 20 tmp = cpu->pc & ~((ARM_IC_ENTRIES_PER_PAGE-1) <<
348 dpavlin 14 ARM_INSTR_ALIGNMENT_SHIFT);
349     tmp += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
350     cpu->cd.arm.tmp_pc = tmp + 12;
351     A__NAME(cpu, ic);
352     #endif
353     }
354    
355    
356     #ifndef A__NOCONDITIONS
357     /* Load/stores with all registers except the PC register: */
358     void A__NAME__eq(struct cpu *cpu, struct arm_instr_call *ic)
359 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_Z) A__NAME(cpu, ic); }
360 dpavlin 14 void A__NAME__ne(struct cpu *cpu, struct arm_instr_call *ic)
361 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
362 dpavlin 14 void A__NAME__cs(struct cpu *cpu, struct arm_instr_call *ic)
363 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_C) A__NAME(cpu, ic); }
364 dpavlin 14 void A__NAME__cc(struct cpu *cpu, struct arm_instr_call *ic)
365 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
366 dpavlin 14 void A__NAME__mi(struct cpu *cpu, struct arm_instr_call *ic)
367 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_N) A__NAME(cpu, ic); }
368 dpavlin 14 void A__NAME__pl(struct cpu *cpu, struct arm_instr_call *ic)
369 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME(cpu, ic); }
370 dpavlin 14 void A__NAME__vs(struct cpu *cpu, struct arm_instr_call *ic)
371 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_V) A__NAME(cpu, ic); }
372 dpavlin 14 void A__NAME__vc(struct cpu *cpu, struct arm_instr_call *ic)
373 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME(cpu, ic); }
374 dpavlin 14
375     void A__NAME__hi(struct cpu *cpu, struct arm_instr_call *ic)
376 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_C &&
377     !(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
378 dpavlin 14 void A__NAME__ls(struct cpu *cpu, struct arm_instr_call *ic)
379 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_Z ||
380     !(cpu->cd.arm.flags & ARM_F_C)) A__NAME(cpu, ic); }
381 dpavlin 14 void A__NAME__ge(struct cpu *cpu, struct arm_instr_call *ic)
382 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
383     ((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
384 dpavlin 14 void A__NAME__lt(struct cpu *cpu, struct arm_instr_call *ic)
385 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
386     ((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME(cpu, ic); }
387 dpavlin 14 void A__NAME__gt(struct cpu *cpu, struct arm_instr_call *ic)
388 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
389     ((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
390     !(cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
391 dpavlin 14 void A__NAME__le(struct cpu *cpu, struct arm_instr_call *ic)
392 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
393     ((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
394     (cpu->cd.arm.flags & ARM_F_Z)) A__NAME(cpu, ic); }
395 dpavlin 14
396    
397     /* Load/stores with the PC register: */
398     void A__NAME_PC__eq(struct cpu *cpu, struct arm_instr_call *ic)
399 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_Z) A__NAME_PC(cpu, ic); }
400 dpavlin 14 void A__NAME_PC__ne(struct cpu *cpu, struct arm_instr_call *ic)
401 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
402 dpavlin 14 void A__NAME_PC__cs(struct cpu *cpu, struct arm_instr_call *ic)
403 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_C) A__NAME_PC(cpu, ic); }
404 dpavlin 14 void A__NAME_PC__cc(struct cpu *cpu, struct arm_instr_call *ic)
405 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
406 dpavlin 14 void A__NAME_PC__mi(struct cpu *cpu, struct arm_instr_call *ic)
407 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_N) A__NAME_PC(cpu, ic); }
408 dpavlin 14 void A__NAME_PC__pl(struct cpu *cpu, struct arm_instr_call *ic)
409 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_N)) A__NAME_PC(cpu, ic); }
410 dpavlin 14 void A__NAME_PC__vs(struct cpu *cpu, struct arm_instr_call *ic)
411 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_V) A__NAME_PC(cpu, ic); }
412 dpavlin 14 void A__NAME_PC__vc(struct cpu *cpu, struct arm_instr_call *ic)
413 dpavlin 20 { if (!(cpu->cd.arm.flags & ARM_F_V)) A__NAME_PC(cpu, ic); }
414 dpavlin 14
415     void A__NAME_PC__hi(struct cpu *cpu, struct arm_instr_call *ic)
416 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_C &&
417     !(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
418 dpavlin 14 void A__NAME_PC__ls(struct cpu *cpu, struct arm_instr_call *ic)
419 dpavlin 20 { if (cpu->cd.arm.flags & ARM_F_Z ||
420     !(cpu->cd.arm.flags & ARM_F_C)) A__NAME_PC(cpu, ic); }
421 dpavlin 14 void A__NAME_PC__ge(struct cpu *cpu, struct arm_instr_call *ic)
422 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
423     ((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
424 dpavlin 14 void A__NAME_PC__lt(struct cpu *cpu, struct arm_instr_call *ic)
425 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
426     ((cpu->cd.arm.flags & ARM_F_V)?1:0)) A__NAME_PC(cpu, ic); }
427 dpavlin 14 void A__NAME_PC__gt(struct cpu *cpu, struct arm_instr_call *ic)
428 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) ==
429     ((cpu->cd.arm.flags & ARM_F_V)?1:0) &&
430     !(cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
431 dpavlin 14 void A__NAME_PC__le(struct cpu *cpu, struct arm_instr_call *ic)
432 dpavlin 20 { if (((cpu->cd.arm.flags & ARM_F_N)?1:0) !=
433     ((cpu->cd.arm.flags & ARM_F_V)?1:0) ||
434     (cpu->cd.arm.flags & ARM_F_Z)) A__NAME_PC(cpu, ic); }
435 dpavlin 14 #endif
436 dpavlin 18
437    
438     #ifdef A__STRD
439     #undef A__STRD
440     #endif

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