--- trunk/src/cpus/cpu_arm_instr.c	2007/10/08 16:19:37	22
+++ trunk/src/cpus/cpu_arm_instr.c	2007/10/08 16:19:56	24
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_arm_instr.c,v 1.60 2006/02/09 22:40:27 debug Exp $
+ *  $Id: cpu_arm_instr.c,v 1.65 2006/06/23 12:49:46 debug Exp $
  *
  *  ARM instructions.
  *
@@ -201,10 +201,8 @@
 
 
 /*
- *  nop:  Do nothing.
  *  invalid:  Invalid instructions end up here.
  */
-X(nop) { }
 X(invalid) {
 	uint32_t low_pc;
 	low_pc = ((size_t)ic - (size_t)
@@ -213,12 +211,19 @@
 	    << ARM_INSTR_ALIGNMENT_SHIFT);
 	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
 
-	fatal("Invalid ARM instruction: pc=0x%08x\n", (int)cpu->pc);
+	fatal("FATAL ERROR: An internal error occured in the ARM"
+	    " dyntrans code. Please contact the author with detailed"
+	    " repro steps on how to trigger this bug. pc = 0x%08"PRIx32"\n",
+	    (uint32_t)cpu->pc);
+	exit(1);
+}
 
-	cpu->running = 0;
-	cpu->running_translated = 0;
-	cpu->n_translated_instrs --;
-	cpu->cd.arm.next_ic = &nothing_call;
+
+/*
+ *  nop:  Do nothing.
+ */
+X(nop)
+{
 }
 
 
@@ -756,7 +761,7 @@
 	cpu->pc &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << ARM_INSTR_ALIGNMENT_SHIFT);
 	cpu->pc += (low_pc << ARM_INSTR_ALIGNMENT_SHIFT);
 	old_pc = cpu->pc;
-	printf("msr_spsr: old pc = 0x%08x\n", old_pc);
+	printf("msr_spsr: old pc = 0x%08"PRIx32"\n", old_pc);
 }
 		exit(1);
 	}
@@ -1320,8 +1325,8 @@
 
 
 /*  Various load/store multiple instructions:  */
-uint32_t *multi_opcode[256];
-void (**multi_opcode_f[256])(struct cpu *, struct arm_instr_call *);
+extern uint32_t *multi_opcode[256];
+extern void (**multi_opcode_f[256])(struct cpu *, struct arm_instr_call *);
 X(multi_0x08b15018);
 X(multi_0x08ac000c__ge);
 X(multi_0x08a05018);
@@ -2455,9 +2460,6 @@
 X(to_be_translated)
 {
 	uint32_t addr, low_pc, iword, imm = 0;
-#ifdef DYNTRANS_BACKEND
-	int simple = 0;
-#endif
 	unsigned char *page;
 	unsigned char ib[4];
 	int condition_code, main_opcode, secondary_opcode, s_bit, rn, rd, r8;
@@ -2638,16 +2640,16 @@
 		    (iword & 0x0fb0f000) == 0x0320f000) {
 			/*  msr: move to [S|C]PSR from a register or
 			    immediate value  */
-			if (rm == ARM_PC) {
-				fatal("msr PC?\n");
-				goto bad;
-			}
 			if (iword & 0x02000000) {
 				if (iword & 0x00400000)
 					ic->f = cond_instr(msr_imm_spsr);
 				else
 					ic->f = cond_instr(msr_imm);
 			} else {
+				if (rm == ARM_PC) {
+					fatal("msr PC?\n");
+					goto bad;
+				}
 				if (iword & 0x00400000)
 					ic->f = cond_instr(msr_spsr);
 				else
@@ -2745,18 +2747,12 @@
 		/*  "mov reg,#0":  */
 		if ((iword & 0x0fff0fff) == 0x03a00000 && rd != ARM_PC) {
 			arm_switch_clear(ic, rd, condition_code);
-#ifdef DYNTRANS_BACKEND
-simple = 1;
-#endif
 			break;
 		}
 
 		/*  "mov reg,#1":  */
 		if ((iword & 0x0fff0fff) == 0x03a00001 && rd != ARM_PC) {
 			arm_switch_mov1(ic, rd, condition_code);
-#ifdef DYNTRANS_BACKEND
-simple = 1;
-#endif
 			break;
 		}
 
@@ -2764,9 +2760,6 @@
 		if ((iword & 0x0ff00fff) == 0x02800001 && rd != ARM_PC
 		    && rn == rd) {
 			arm_switch_add1(ic, rd, condition_code);
-#ifdef DYNTRANS_BACKEND
-simple = 1;
-#endif
 			break;
 		}