/[gxemul]/trunk/src/cpus/cpu_arm_coproc.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/cpus/cpu_arm_coproc.c

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 33 by dpavlin, Mon Oct 8 16:20:10 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: cpu_arm_coproc.c,v 1.24 2006/06/24 21:47:23 debug Exp $   *  $Id: cpu_arm_coproc.c,v 1.28 2007/02/05 16:49:21 debug Exp $
29   *   *
30   *  ARM coprocessor emulation.   *  ARM coprocessor emulation.
31   */   */
# Line 374  void arm_coproc_i80321_6(struct cpu *cpu Line 374  void arm_coproc_i80321_6(struct cpu *cpu
374                          else {                          else {
375                                  /*  Writing clears interrupts:  */                                  /*  Writing clears interrupts:  */
376                                  cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd];                                  cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd];
377    
378                                  if (!(cpu->cd.arm.tisr & TISR_TMR0))                                  if (!(cpu->cd.arm.tisr & TISR_TMR0))
379                                          cpu_interrupt_ack(cpu, 9);  /* TMR0 */                                          INTERRUPT_DEASSERT(
380                                                cpu->cd.arm.tmr0_irq);
381                                  if (!(cpu->cd.arm.tisr & TISR_TMR1))                                  if (!(cpu->cd.arm.tisr & TISR_TMR1))
382                                          cpu_interrupt_ack(cpu, 10); /* TMR1 */                                          INTERRUPT_DEASSERT(
383                                                cpu->cd.arm.tmr1_irq);
384                          }                          }
385                          break;                          break;
386                  case 7: /*  wdtcr:  */                  case 7: /*  wdtcr:  */
Legend:
Removed from v.33  
changed lines
  Added in v.34
  ViewVC Help
Powered by ViewVC 1.1.26