25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm_coproc.c,v 1.23 2006/02/26 20:11:14 debug Exp $ |
* $Id: cpu_arm_coproc.c,v 1.24 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
* |
30 |
* ARM coprocessor emulation. |
* ARM coprocessor emulation. |
31 |
*/ |
*/ |
139 |
(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
140 |
debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
141 |
ARM_CONTROL_MMU? "enabling" : "disabling"); |
ARM_CONTROL_MMU? "enabling" : "disabling"); |
142 |
cpu->translate_address = |
cpu->translate_v2p = |
143 |
cpu->cd.arm.control & ARM_CONTROL_MMU? |
cpu->cd.arm.control & ARM_CONTROL_MMU? |
144 |
arm_translate_address_mmu : arm_translate_address; |
arm_translate_v2p_mmu : arm_translate_v2p; |
145 |
} |
} |
146 |
if ((old_control & ARM_CONTROL_ALIGN) != |
if ((old_control & ARM_CONTROL_ALIGN) != |
147 |
(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |
(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |