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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm_coproc.c,v 1.24 2006/06/24 21:47:23 debug Exp $ |
* $Id: cpu_arm_coproc.c,v 1.28 2007/02/05 16:49:21 debug Exp $ |
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* |
* |
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* ARM coprocessor emulation. |
* ARM coprocessor emulation. |
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*/ |
*/ |
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else { |
else { |
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/* Writing clears interrupts: */ |
/* Writing clears interrupts: */ |
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cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd]; |
cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd]; |
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|
|
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if (!(cpu->cd.arm.tisr & TISR_TMR0)) |
if (!(cpu->cd.arm.tisr & TISR_TMR0)) |
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cpu_interrupt_ack(cpu, 9); /* TMR0 */ |
INTERRUPT_DEASSERT( |
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cpu->cd.arm.tmr0_irq); |
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if (!(cpu->cd.arm.tisr & TISR_TMR1)) |
if (!(cpu->cd.arm.tisr & TISR_TMR1)) |
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cpu_interrupt_ack(cpu, 10); /* TMR1 */ |
INTERRUPT_DEASSERT( |
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cpu->cd.arm.tmr1_irq); |
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} |
} |
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break; |
break; |
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case 7: /* wdtcr: */ |
case 7: /* wdtcr: */ |