/[gxemul]/trunk/src/cpus/cpu_arm_coproc.c
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Contents of /trunk/src/cpus/cpu_arm_coproc.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 7784 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_arm_coproc.c,v 1.15 2005/11/05 21:59:01 debug Exp $
29 *
30 * ARM coprocessor emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "misc.h"
40 #include "symbol.h"
41
42
43 /*
44 * arm_coproc_15():
45 *
46 * The system control coprocessor.
47 */
48 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
49 int crn, int crm, int rd)
50 {
51 uint32_t old_control;
52
53 /* Some sanity checks: */
54 if (opcode1 != 0) {
55 fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1);
56 exit(1);
57 }
58 if (rd == ARM_PC) {
59 fatal("arm_coproc_15: rd = PC\n");
60 exit(1);
61 }
62
63 switch (crn) {
64
65 case 0: /* Main ID register: */
66 if (opcode2 != 0)
67 fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n",
68 opcode2);
69 if (l_bit)
70 cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
71 else
72 fatal("[ arm_coproc_15: attempt to write to cr0? ]\n");
73 break;
74
75 case 1: /* Control Register: */
76 if (l_bit) {
77 cpu->cd.arm.r[rd] = cpu->cd.arm.control;
78 return;
79 }
80 /*
81 * Write to control: Check each bit individually:
82 */
83 old_control = cpu->cd.arm.control;
84 cpu->cd.arm.control = cpu->cd.arm.r[rd];
85 if ((old_control & ARM_CONTROL_MMU) !=
86 (cpu->cd.arm.control & ARM_CONTROL_MMU)) {
87 debug("[ %s the MMU ]\n", cpu->cd.arm.control &
88 ARM_CONTROL_MMU? "enabling" : "disabling");
89 cpu->translate_address =
90 cpu->cd.arm.control & ARM_CONTROL_MMU?
91 arm_translate_address_mmu : arm_translate_address;
92 }
93 if ((old_control & ARM_CONTROL_ALIGN) !=
94 (cpu->cd.arm.control & ARM_CONTROL_ALIGN))
95 debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
96 ARM_CONTROL_ALIGN? "enabling" : "disabling");
97 if ((old_control & ARM_CONTROL_CACHE) !=
98 (cpu->cd.arm.control & ARM_CONTROL_CACHE))
99 debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
100 ARM_CONTROL_CACHE? "enabling" : "disabling");
101 if ((old_control & ARM_CONTROL_WBUFFER) !=
102 (cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
103 debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
104 ARM_CONTROL_WBUFFER? "enabling" : "disabling");
105 if ((old_control & ARM_CONTROL_BIG) !=
106 (cpu->cd.arm.control & ARM_CONTROL_BIG)) {
107 fatal("ERROR: Trying to switch endianness. Not "
108 "supported yet.\n");
109 exit(1);
110 }
111 if ((old_control & ARM_CONTROL_ICACHE) !=
112 (cpu->cd.arm.control & ARM_CONTROL_ICACHE))
113 debug("[ %s the icache ]\n", cpu->cd.arm.control &
114 ARM_CONTROL_ICACHE? "enabling" : "disabling");
115 /* TODO: More bits. */
116 break;
117
118 case 2: /* Translation Table Base register: */
119 /* NOTE: 16 KB aligned. */
120 if (l_bit)
121 cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
122 else {
123 cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
124 if (cpu->cd.arm.ttb & 0x3fff)
125 fatal("[ WARNING! low bits of new TTB non-"
126 "zero? 0x%08x ]\n", cpu->cd.arm.ttb);
127 cpu->cd.arm.ttb &= 0xffffc000;
128 }
129 break;
130
131 case 3: /* Domain Access Control Register: */
132 if (l_bit)
133 cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
134 else
135 cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
136 break;
137
138 case 5: /* Fault Status Register: */
139 /* Note: Only the lowest 8 bits are defined. */
140 if (l_bit)
141 cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
142 else
143 cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
144 break;
145
146 case 6: /* Fault Address Register: */
147 if (l_bit)
148 cpu->cd.arm.r[rd] = cpu->cd.arm.far;
149 else
150 cpu->cd.arm.far = cpu->cd.arm.r[rd];
151 break;
152
153 case 7: /* Cache functions: */
154 if (l_bit) {
155 fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
156 return;
157 }
158 /* debug("[ arm_coproc_15: cache op: TODO ]\n"); */
159 /* TODO: */
160 break;
161
162 case 8: /* TLB functions: */
163 if (l_bit) {
164 fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
165 return;
166 }
167 /* fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
168 opcode2, crm, cpu->cd.arm.r[rd]); */
169 if (opcode2 == 0)
170 cpu->invalidate_translation_caches(cpu, 0,
171 INVALIDATE_ALL);
172 else
173 cpu->invalidate_translation_caches(cpu,
174 cpu->cd.arm.r[rd], INVALIDATE_VADDR);
175 break;
176
177 case 9: /* Cache lockdown: */
178 /* TODO */
179 break;
180
181 case 13:/* Process ID Register: */
182 if (opcode2 != 0)
183 fatal("[ arm_coproc_15: PID access, but opcode2 "
184 "= %i? (should be 0) ]\n", opcode2);
185 if (crm != 0)
186 fatal("[ arm_coproc_15: PID access, but crm "
187 "= %i? (should be 0) ]\n", crm);
188 if (l_bit)
189 cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
190 else
191 cpu->cd.arm.pid = cpu->cd.arm.r[rd];
192 if (cpu->cd.arm.pid != 0) {
193 fatal("ARM TODO: pid!=0. Fast Context Switch"
194 " Extension not implemented yet\n");
195 exit(1);
196 }
197 break;
198
199 case 15:/* IMPLEMENTATION DEPENDENT! */
200 debug("[ arm_coproc_15: TODO: IMPLEMENTATION DEPENDENT! ]\n");
201 break;
202
203 default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn);
204 fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
205 opcode1, opcode2, crm, rd, l_bit);
206 exit(1);
207 }
208 }
209
210
211 /*****************************************************************************/
212
213
214 /*
215 * arm_coproc_i80321():
216 *
217 * Intel 80321 coprocessor.
218 */
219 void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
220 int crn, int crm, int rd)
221 {
222 switch (crm) {
223 case 0: fatal("[ 80321: crm 0: TODO ]\n");
224 break;
225 case 1: fatal("[ 80321: crm 1: TODO ]\n");
226 switch (crn) {
227 case 0: /* tmr0: */
228 break;
229 case 2: /* tcr0: */
230 break;
231 case 4: /* trr0: */
232 break;
233 case 6: /* tisr: */
234 break;
235 default:fatal("arm_coproc_i80321: unimplemented crn = %i\n",
236 crn);
237 fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
238 opcode1, opcode2, crm, rd, l_bit);
239 exit(1);
240 }
241 break;
242 default:fatal("arm_coproc_i80321: unimplemented opcode1=%i opcode2=%i"
243 " crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
244 crn, crm, rd, l_bit);
245 exit(1);
246 }
247 }
248
249
250 /*
251 * arm_coproc_i80321_14():
252 *
253 * Intel 80321 coprocessor 14.
254 */
255 void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
256 int crn, int crm, int rd)
257 {
258 switch (crm) {
259 case 0: fatal("[ 80321_14: crm 0: TODO ]\n");
260 break;
261 default:fatal("arm_coproc_i80321_14: unimplemented opcode1=%i opcode2="
262 "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2,
263 crn, crm, rd, l_bit);
264 exit(1);
265 }
266 }
267

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