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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm_coproc.c,v 1.10 2005/10/07 22:10:51 debug Exp $ |
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* |
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* ARM coprocessor emulation. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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|
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#include "cpu.h" |
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#include "misc.h" |
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#include "symbol.h" |
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|
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|
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/* |
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* arm_coproc_15(): |
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* |
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* The system control coprocessor. |
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*/ |
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void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd) |
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{ |
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uint32_t old_control; |
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|
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/* Some sanity checks: */ |
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if (opcode1 != 0) { |
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fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1); |
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exit(1); |
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} |
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if (rd == ARM_PC) { |
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fatal("arm_coproc_15: rd = PC\n"); |
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exit(1); |
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} |
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|
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switch (crn) { |
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|
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case 0: /* Main ID register: */ |
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if (opcode2 != 0) |
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fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n", |
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opcode2); |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id; |
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else |
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fatal("[ arm_coproc_15: attempt to write to cr0? ]\n"); |
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break; |
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|
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case 1: /* Control Register: */ |
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if (l_bit) { |
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cpu->cd.arm.r[rd] = cpu->cd.arm.control; |
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return; |
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} |
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/* |
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* Write to control: Check each bit individually: |
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*/ |
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old_control = cpu->cd.arm.control; |
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cpu->cd.arm.control = cpu->cd.arm.r[rd]; |
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if ((old_control & ARM_CONTROL_MMU) != |
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(cpu->cd.arm.control & ARM_CONTROL_MMU)) |
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debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_MMU? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_ALIGN) != |
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(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |
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debug("[ %s alignment checks ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_ALIGN? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_CACHE) != |
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(cpu->cd.arm.control & ARM_CONTROL_CACHE)) |
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debug("[ %s the [data] cache ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_CACHE? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_WBUFFER) != |
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(cpu->cd.arm.control & ARM_CONTROL_WBUFFER)) |
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debug("[ %s the write buffer ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_WBUFFER? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_BIG) != |
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(cpu->cd.arm.control & ARM_CONTROL_BIG)) { |
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fatal("ERROR: Trying to switch endianness. Not " |
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"supported yet.\n"); |
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exit(1); |
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} |
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if ((old_control & ARM_CONTROL_ICACHE) != |
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(cpu->cd.arm.control & ARM_CONTROL_ICACHE)) |
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debug("[ %s the icache ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_ICACHE? "enabling" : "disabling"); |
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/* TODO: More bits. */ |
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break; |
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|
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case 2: /* Translation Table Base register: */ |
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/* NOTE: 16 KB aligned. */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000; |
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else { |
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cpu->cd.arm.ttb = cpu->cd.arm.r[rd]; |
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if (cpu->cd.arm.ttb & 0x3fff) |
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fatal("[ WARNING! low bits of new TTB non-" |
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"zero? 0x%08x ]\n", cpu->cd.arm.ttb); |
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cpu->cd.arm.ttb &= 0xffffc000; |
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} |
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break; |
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|
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case 3: /* Domain Access Control Register: */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.dacr; |
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else |
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cpu->cd.arm.dacr = cpu->cd.arm.r[rd]; |
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break; |
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|
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case 5: /* Fault Status Register: */ |
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/* Note: Only the lowest 8 bits are defined. */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff; |
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else |
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cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff; |
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break; |
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|
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case 6: /* Fault Address Register: */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.far; |
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else |
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cpu->cd.arm.far = cpu->cd.arm.r[rd]; |
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break; |
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|
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case 7: /* Cache functions: */ |
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if (l_bit) { |
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fatal("[ arm_coproc_15: attempt to read cr7? ]\n"); |
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return; |
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} |
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/* debug("[ arm_coproc_15: cache op: TODO ]\n"); */ |
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/* TODO: */ |
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break; |
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|
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case 8: /* TLB functions: */ |
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if (l_bit) { |
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fatal("[ arm_coproc_15: attempt to read cr8? ]\n"); |
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return; |
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} |
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/* fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n", |
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opcode2, crm, cpu->cd.arm.r[rd]); */ |
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if (opcode2 == 0) |
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cpu->invalidate_translation_caches_paddr(cpu, 0, |
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INVALIDATE_ALL); |
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else |
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cpu->invalidate_translation_caches_paddr(cpu, |
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cpu->cd.arm.r[rd], INVALIDATE_VADDR); |
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break; |
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|
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case 13:/* Process ID Register: */ |
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if (opcode2 != 0) |
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fatal("[ arm_coproc_15: PID access, but opcode2 " |
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"= %i? (should be 0) ]\n", opcode2); |
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if (crm != 0) |
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fatal("[ arm_coproc_15: PID access, but crm " |
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"= %i? (should be 0) ]\n", crm); |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.pid; |
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else |
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cpu->cd.arm.pid = cpu->cd.arm.r[rd]; |
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if (cpu->cd.arm.pid != 0) { |
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fatal("ARM TODO: pid!=0. Fast Context Switch" |
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" Extension not implemented yet\n"); |
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exit(1); |
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} |
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break; |
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|
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case 15:/* IMPLEMENTATION DEPENDANT! */ |
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fatal("[ arm_coproc_15: TODO: IMPLEMENTATION DEPENDANT! ]\n"); |
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break; |
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|
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default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn); |
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fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n", |
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opcode1, opcode2, crm, rd, l_bit); |
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exit(1); |
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} |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* arm_coproc_i80321(): |
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* |
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* Intel 80321 coprocessor. |
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*/ |
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void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd) |
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{ |
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switch (crm) { |
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case 0: fatal("[ 80321: crm 0: TODO ]\n"); |
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break; |
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case 1: fatal("[ 80321: crm 1: TODO ]\n"); |
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switch (crn) { |
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case 0: /* tmr0: */ |
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break; |
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case 2: /* tcr0: */ |
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break; |
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case 4: /* trr0: */ |
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break; |
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case 6: /* tisr: */ |
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break; |
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default:fatal("arm_coproc_i80321: unimplemented crn = %i\n", |
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crn); |
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fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n", |
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opcode1, opcode2, crm, rd, l_bit); |
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exit(1); |
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} |
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break; |
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default:fatal("arm_coproc_i80321: unimplemented opcode1=%i opcode2=%i" |
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" crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, |
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crn, crm, rd, l_bit); |
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exit(1); |
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} |
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} |
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|
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|
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/* |
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* arm_coproc_i80321_14(): |
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* |
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* Intel 80321 coprocessor 14. |
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*/ |
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void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd) |
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{ |
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switch (crm) { |
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case 0: fatal("[ 80321_14: crm 0: TODO ]\n"); |
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break; |
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default:fatal("arm_coproc_i80321_14: unimplemented opcode1=%i opcode2=" |
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"%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, |
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crn, crm, rd, l_bit); |
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exit(1); |
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} |
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} |
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|