25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm_coproc.c,v 1.22 2006/02/17 18:38:30 debug Exp $ |
* $Id: cpu_arm_coproc.c,v 1.24 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
* |
30 |
* ARM coprocessor emulation. |
* ARM coprocessor emulation. |
31 |
*/ |
*/ |
37 |
#include <ctype.h> |
#include <ctype.h> |
38 |
|
|
39 |
#include "cpu.h" |
#include "cpu.h" |
40 |
|
#include "machine.h" |
41 |
#include "misc.h" |
#include "misc.h" |
42 |
#include "symbol.h" |
#include "symbol.h" |
43 |
|
|
139 |
(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
140 |
debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
141 |
ARM_CONTROL_MMU? "enabling" : "disabling"); |
ARM_CONTROL_MMU? "enabling" : "disabling"); |
142 |
cpu->translate_address = |
cpu->translate_v2p = |
143 |
cpu->cd.arm.control & ARM_CONTROL_MMU? |
cpu->cd.arm.control & ARM_CONTROL_MMU? |
144 |
arm_translate_address_mmu : arm_translate_address; |
arm_translate_v2p_mmu : arm_translate_v2p; |
145 |
} |
} |
146 |
if ((old_control & ARM_CONTROL_ALIGN) != |
if ((old_control & ARM_CONTROL_ALIGN) != |
147 |
(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |
(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |
292 |
switch (crm) { |
switch (crm) { |
293 |
|
|
294 |
case 0: switch (crn) { |
case 0: switch (crn) { |
295 |
case 0: if (l_bit) |
case 0: if (l_bit) { |
296 |
cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten; |
cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten; |
297 |
else |
fatal("TODO: XScale read from inten?\n"); |
298 |
|
exit(1); |
299 |
|
} else |
300 |
cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd]; |
cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd]; |
301 |
break; |
break; |
302 |
case 4: if (l_bit) |
case 4: if (l_bit) |
322 |
} |
} |
323 |
break; |
break; |
324 |
|
|
325 |
case 1: |
case 1: /* fatal("TIMER opcode1=%i opcode2=%i crn=" |
326 |
/* fatal("TIMER opcode1=%i opcode2=%i crn=" |
"%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit); */ |
|
"%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit); */ |
|
327 |
|
|
328 |
switch (crn) { |
switch (crn) { |
329 |
case 0: /* tmr0: */ |
case 0: /* tmr0: */ |