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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_arm_coproc.c,v 1.22 2006/02/17 18:38:30 debug Exp $ |
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dpavlin |
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* |
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* ARM coprocessor emulation. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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dpavlin |
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#include <unistd.h> |
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dpavlin |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "misc.h" |
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#include "symbol.h" |
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dpavlin |
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#include "i80321reg.h" |
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dpavlin |
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|
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dpavlin |
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|
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dpavlin |
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/* |
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* arm_coproc_15(): |
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* |
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* The system control coprocessor. |
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*/ |
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void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd) |
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{ |
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uint32_t old_control; |
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/* Some sanity checks: */ |
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if (opcode1 != 0) { |
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fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1); |
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exit(1); |
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} |
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if (rd == ARM_PC) { |
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fatal("arm_coproc_15: rd = PC\n"); |
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exit(1); |
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} |
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switch (crn) { |
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dpavlin |
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case 0: /* |
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* Main ID register (and Cache Type register, on XScale) |
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* |
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* Writes are supposed to be ignored, according to Intel docs. |
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*/ |
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switch (opcode2) { |
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case 0: if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id; |
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else |
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fatal("[ arm_coproc_15: attempt to write " |
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"to the Main ID register? ]\n"); |
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break; |
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case 1: if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.cachetype; |
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else |
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fatal("[ arm_coproc_15: attempt to write " |
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"to the Cache Type register? ]\n"); |
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break; |
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default:fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n", |
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opcode2); |
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exit(1); |
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} |
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break; |
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case 1: /* Control Register: */ |
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if (l_bit) { |
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/* Load from the normal/aux control register: */ |
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switch (opcode2) { |
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case 0: cpu->cd.arm.r[rd] = cpu->cd.arm.control; |
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break; |
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case 1: cpu->cd.arm.r[rd] = cpu->cd.arm.auxctrl; |
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break; |
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default:fatal("Unimplemented opcode2 = %i\n", opcode2); |
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fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n", |
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opcode1, crn, crm, rd, l_bit); |
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exit(1); |
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} |
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return; |
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} |
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|
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if (opcode2 == 1) { |
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/* Write to auxctrl: */ |
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old_control = cpu->cd.arm.auxctrl; |
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cpu->cd.arm.auxctrl = cpu->cd.arm.r[rd]; |
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if ((old_control & ARM_AUXCTRL_MD) != |
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(cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)) { |
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debug("[ setting the minidata cache attribute" |
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" to 0x%x ]\n", (cpu->cd.arm.auxctrl & |
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ARM_AUXCTRL_MD) >> ARM_AUXCTRL_MD_SHIFT); |
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} |
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if ((old_control & ARM_AUXCTRL_K) != |
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(cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)) { |
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debug("[ %s write buffer coalescing ]\n", |
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cpu->cd.arm.auxctrl & ARM_AUXCTRL_K? |
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"Disabling" : "Enabling"); |
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} |
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return; |
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} else if (opcode2 != 0) { |
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fatal("Unimplemented write, opcode2 = %i\n", opcode2); |
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fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n", |
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opcode1, crn, crm, rd, l_bit); |
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exit(1); |
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} |
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dpavlin |
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/* |
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* Write to control: Check each bit individually: |
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*/ |
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old_control = cpu->cd.arm.control; |
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cpu->cd.arm.control = cpu->cd.arm.r[rd]; |
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if ((old_control & ARM_CONTROL_MMU) != |
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dpavlin |
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(cpu->cd.arm.control & ARM_CONTROL_MMU)) { |
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dpavlin |
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debug("[ %s the MMU ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_MMU? "enabling" : "disabling"); |
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dpavlin |
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cpu->translate_address = |
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cpu->cd.arm.control & ARM_CONTROL_MMU? |
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arm_translate_address_mmu : arm_translate_address; |
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} |
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dpavlin |
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if ((old_control & ARM_CONTROL_ALIGN) != |
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(cpu->cd.arm.control & ARM_CONTROL_ALIGN)) |
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debug("[ %s alignment checks ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_ALIGN? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_CACHE) != |
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(cpu->cd.arm.control & ARM_CONTROL_CACHE)) |
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debug("[ %s the [data] cache ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_CACHE? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_WBUFFER) != |
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(cpu->cd.arm.control & ARM_CONTROL_WBUFFER)) |
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debug("[ %s the write buffer ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_WBUFFER? "enabling" : "disabling"); |
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if ((old_control & ARM_CONTROL_BIG) != |
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(cpu->cd.arm.control & ARM_CONTROL_BIG)) { |
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fatal("ERROR: Trying to switch endianness. Not " |
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"supported yet.\n"); |
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exit(1); |
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} |
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if ((old_control & ARM_CONTROL_ICACHE) != |
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(cpu->cd.arm.control & ARM_CONTROL_ICACHE)) |
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debug("[ %s the icache ]\n", cpu->cd.arm.control & |
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ARM_CONTROL_ICACHE? "enabling" : "disabling"); |
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/* TODO: More bits. */ |
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break; |
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case 2: /* Translation Table Base register: */ |
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/* NOTE: 16 KB aligned. */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000; |
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else { |
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cpu->cd.arm.ttb = cpu->cd.arm.r[rd]; |
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if (cpu->cd.arm.ttb & 0x3fff) |
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fatal("[ WARNING! low bits of new TTB non-" |
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"zero? 0x%08x ]\n", cpu->cd.arm.ttb); |
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cpu->cd.arm.ttb &= 0xffffc000; |
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} |
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break; |
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case 3: /* Domain Access Control Register: */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.dacr; |
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else |
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cpu->cd.arm.dacr = cpu->cd.arm.r[rd]; |
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break; |
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case 5: /* Fault Status Register: */ |
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/* Note: Only the lowest 8 bits are defined. */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff; |
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else |
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cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff; |
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break; |
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case 6: /* Fault Address Register: */ |
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if (l_bit) |
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cpu->cd.arm.r[rd] = cpu->cd.arm.far; |
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else |
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cpu->cd.arm.far = cpu->cd.arm.r[rd]; |
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break; |
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case 7: /* Cache functions: */ |
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if (l_bit) { |
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fatal("[ arm_coproc_15: attempt to read cr7? ]\n"); |
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return; |
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} |
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/* debug("[ arm_coproc_15: cache op: TODO ]\n"); */ |
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/* TODO: */ |
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break; |
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case 8: /* TLB functions: */ |
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if (l_bit) { |
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fatal("[ arm_coproc_15: attempt to read cr8? ]\n"); |
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return; |
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} |
219 |
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/* fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n", |
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opcode2, crm, cpu->cd.arm.r[rd]); */ |
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if (opcode2 == 0) |
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dpavlin |
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cpu->invalidate_translation_caches(cpu, 0, |
223 |
dpavlin |
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INVALIDATE_ALL); |
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else |
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dpavlin |
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cpu->invalidate_translation_caches(cpu, |
226 |
dpavlin |
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cpu->cd.arm.r[rd], INVALIDATE_VADDR); |
227 |
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break; |
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229 |
dpavlin |
20 |
case 9: /* Cache lockdown: */ |
230 |
dpavlin |
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fatal("[ arm_coproc_15: cache lockdown: TODO ]\n"); |
231 |
dpavlin |
20 |
/* TODO */ |
232 |
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break; |
233 |
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234 |
dpavlin |
14 |
case 13:/* Process ID Register: */ |
235 |
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if (opcode2 != 0) |
236 |
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fatal("[ arm_coproc_15: PID access, but opcode2 " |
237 |
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"= %i? (should be 0) ]\n", opcode2); |
238 |
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if (crm != 0) |
239 |
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fatal("[ arm_coproc_15: PID access, but crm " |
240 |
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"= %i? (should be 0) ]\n", crm); |
241 |
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if (l_bit) |
242 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.pid; |
243 |
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else |
244 |
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cpu->cd.arm.pid = cpu->cd.arm.r[rd]; |
245 |
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if (cpu->cd.arm.pid != 0) { |
246 |
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fatal("ARM TODO: pid!=0. Fast Context Switch" |
247 |
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" Extension not implemented yet\n"); |
248 |
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exit(1); |
249 |
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} |
250 |
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break; |
251 |
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252 |
dpavlin |
22 |
/* case 14: */ |
253 |
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/* Breakpoint registers on XScale (possibly others?) */ |
254 |
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/* TODO */ |
255 |
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/* break; */ |
256 |
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257 |
dpavlin |
18 |
case 15:/* IMPLEMENTATION DEPENDENT! */ |
258 |
dpavlin |
22 |
switch (crm) { |
259 |
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case 1: /* |
260 |
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* On XScale (and others? TODO), this is the |
261 |
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* CoProcessor Access Register. Note/TODO: This isn't |
262 |
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* really used throughout the rest of the code yet. |
263 |
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*/ |
264 |
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if (l_bit) |
265 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.cpar; |
266 |
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else |
267 |
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cpu->cd.arm.cpar = cpu->cd.arm.r[rd]; |
268 |
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break; |
269 |
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default:fatal("[ arm_coproc_15: TODO: IMPLEMENTATION " |
270 |
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"DEPENDENT! ]\n"); |
271 |
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exit(1); |
272 |
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} |
273 |
dpavlin |
14 |
break; |
274 |
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275 |
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default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn); |
276 |
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fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n", |
277 |
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opcode1, opcode2, crm, rd, l_bit); |
278 |
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exit(1); |
279 |
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} |
280 |
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} |
281 |
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282 |
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283 |
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/* |
284 |
dpavlin |
22 |
* arm_coproc_i80321_6(): |
285 |
dpavlin |
14 |
* |
286 |
dpavlin |
22 |
* Intel 80321 coprocessor 6. |
287 |
dpavlin |
14 |
*/ |
288 |
dpavlin |
22 |
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
289 |
dpavlin |
14 |
int crn, int crm, int rd) |
290 |
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{ |
291 |
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switch (crm) { |
292 |
dpavlin |
22 |
|
293 |
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case 0: switch (crn) { |
294 |
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case 0: if (l_bit) |
295 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten; |
296 |
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else |
297 |
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cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd]; |
298 |
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break; |
299 |
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case 4: if (l_bit) |
300 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isteer; |
301 |
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else { |
302 |
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cpu->cd.arm.i80321_isteer = cpu->cd.arm.r[rd]; |
303 |
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if (cpu->cd.arm.r[rd] != 0) { |
304 |
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fatal("ARM xscale interrupt steering" |
305 |
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" is not yet implemented\n"); |
306 |
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exit(1); |
307 |
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} |
308 |
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} |
309 |
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break; |
310 |
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case 8: if (l_bit) |
311 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isrc; |
312 |
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else { |
313 |
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cpu->cd.arm.i80321_isrc = cpu->cd.arm.r[rd]; |
314 |
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fatal("TODO: XScale int ack?\n"); |
315 |
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exit(1); |
316 |
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} |
317 |
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break; |
318 |
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default:goto unknown; |
319 |
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} |
320 |
dpavlin |
14 |
break; |
321 |
dpavlin |
22 |
|
322 |
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case 1: |
323 |
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/* fatal("TIMER opcode1=%i opcode2=%i crn=" |
324 |
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"%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit); */ |
325 |
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|
326 |
dpavlin |
14 |
switch (crn) { |
327 |
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case 0: /* tmr0: */ |
328 |
dpavlin |
22 |
if (l_bit) |
329 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.tmr0; |
330 |
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else |
331 |
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cpu->cd.arm.tmr0 = cpu->cd.arm.r[rd]; |
332 |
dpavlin |
14 |
break; |
333 |
dpavlin |
22 |
case 1: /* tmr1: */ |
334 |
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if (l_bit) |
335 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.tmr1; |
336 |
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else |
337 |
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cpu->cd.arm.tmr1 = cpu->cd.arm.r[rd]; |
338 |
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break; |
339 |
dpavlin |
14 |
case 2: /* tcr0: */ |
340 |
dpavlin |
22 |
if (l_bit) { |
341 |
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/* NOTE/TODO: Ugly hack: timer increment */ |
342 |
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cpu->cd.arm.tcr0 ++; |
343 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.tcr0; |
344 |
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} else { |
345 |
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cpu->cd.arm.tcr0 = cpu->cd.arm.r[rd]; |
346 |
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} |
347 |
dpavlin |
14 |
break; |
348 |
dpavlin |
22 |
case 3: /* tcr1: */ |
349 |
|
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if (l_bit) { |
350 |
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/* NOTE/TODO: Ugly hack: timer increment */ |
351 |
|
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cpu->cd.arm.tcr1 ++; |
352 |
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cpu->cd.arm.r[rd] = cpu->cd.arm.tcr1; |
353 |
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} else { |
354 |
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cpu->cd.arm.tcr1 = cpu->cd.arm.r[rd]; |
355 |
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} |
356 |
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break; |
357 |
dpavlin |
14 |
case 4: /* trr0: */ |
358 |
dpavlin |
22 |
if (l_bit) |
359 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.trr0; |
360 |
|
|
else |
361 |
|
|
cpu->cd.arm.trr0 = cpu->cd.arm.r[rd]; |
362 |
dpavlin |
14 |
break; |
363 |
dpavlin |
22 |
case 5: /* trr1: */ |
364 |
|
|
if (l_bit) |
365 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.trr1; |
366 |
|
|
else |
367 |
|
|
cpu->cd.arm.trr1 = cpu->cd.arm.r[rd]; |
368 |
|
|
break; |
369 |
dpavlin |
14 |
case 6: /* tisr: */ |
370 |
dpavlin |
22 |
if (l_bit) |
371 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.tisr; |
372 |
|
|
else { |
373 |
|
|
/* Writing clears interrupts: */ |
374 |
|
|
cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd]; |
375 |
|
|
if (!(cpu->cd.arm.tisr & TISR_TMR0)) |
376 |
|
|
cpu_interrupt_ack(cpu, 9); /* TMR0 */ |
377 |
|
|
if (!(cpu->cd.arm.tisr & TISR_TMR1)) |
378 |
|
|
cpu_interrupt_ack(cpu, 10); /* TMR1 */ |
379 |
|
|
} |
380 |
dpavlin |
14 |
break; |
381 |
dpavlin |
22 |
case 7: /* wdtcr: */ |
382 |
|
|
if (l_bit) |
383 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.wdtcr; |
384 |
|
|
else |
385 |
|
|
cpu->cd.arm.wdtcr = cpu->cd.arm.r[rd]; |
386 |
|
|
break; |
387 |
|
|
default:goto unknown; |
388 |
dpavlin |
14 |
} |
389 |
|
|
break; |
390 |
dpavlin |
22 |
|
391 |
|
|
default:goto unknown; |
392 |
dpavlin |
14 |
} |
393 |
dpavlin |
22 |
|
394 |
|
|
return; |
395 |
|
|
|
396 |
|
|
unknown: |
397 |
|
|
fatal("arm_coproc_i80321_6: unimplemented opcode1=%i opcode2=%i crn=" |
398 |
|
|
"%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit); |
399 |
|
|
exit(1); |
400 |
dpavlin |
14 |
} |
401 |
|
|
|
402 |
|
|
|
403 |
|
|
/* |
404 |
dpavlin |
22 |
* arm_coproc_xscale_14(): |
405 |
dpavlin |
14 |
* |
406 |
dpavlin |
22 |
* XScale coprocessor 14, Performance Monitoring Unit. |
407 |
dpavlin |
14 |
*/ |
408 |
dpavlin |
22 |
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
409 |
dpavlin |
14 |
int crn, int crm, int rd) |
410 |
|
|
{ |
411 |
dpavlin |
22 |
if (opcode2 != 0) { |
412 |
|
|
fatal("TODO: opcode2 = %i\n", opcode2); |
413 |
|
|
goto unknown; |
414 |
|
|
} |
415 |
|
|
|
416 |
dpavlin |
14 |
switch (crm) { |
417 |
dpavlin |
22 |
|
418 |
|
|
case 0: switch (crn) { |
419 |
|
|
case 0: if (l_bit) |
420 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmnc; |
421 |
|
|
else |
422 |
|
|
cpu->cd.arm.xsc1_pmnc = cpu->cd.arm.r[rd]; |
423 |
|
|
break; |
424 |
|
|
case 1: if (l_bit) |
425 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_ccnt; |
426 |
|
|
else |
427 |
|
|
cpu->cd.arm.xsc1_ccnt = cpu->cd.arm.r[rd]; |
428 |
|
|
break; |
429 |
|
|
case 2: if (l_bit) |
430 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn0; |
431 |
|
|
else |
432 |
|
|
cpu->cd.arm.xsc1_pmn0 = cpu->cd.arm.r[rd]; |
433 |
|
|
break; |
434 |
|
|
case 3: if (l_bit) |
435 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn1; |
436 |
|
|
else |
437 |
|
|
cpu->cd.arm.xsc1_pmn1 = cpu->cd.arm.r[rd]; |
438 |
|
|
break; |
439 |
|
|
case 7: /* UNIMPLEMENTED!!! TODO */ |
440 |
|
|
/* Possibly some kind of idle or sleep function. */ |
441 |
|
|
break; |
442 |
|
|
default:goto unknown; |
443 |
|
|
} |
444 |
dpavlin |
14 |
break; |
445 |
dpavlin |
22 |
|
446 |
|
|
case 1: switch (crn) { |
447 |
|
|
case 0: if (l_bit) |
448 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmnc; |
449 |
|
|
else |
450 |
|
|
cpu->cd.arm.xsc2_pmnc = cpu->cd.arm.r[rd]; |
451 |
|
|
break; |
452 |
|
|
case 1: if (l_bit) |
453 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_ccnt; |
454 |
|
|
else |
455 |
|
|
cpu->cd.arm.xsc2_ccnt = cpu->cd.arm.r[rd]; |
456 |
|
|
break; |
457 |
|
|
case 4: if (l_bit) |
458 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_inten; |
459 |
|
|
else |
460 |
|
|
cpu->cd.arm.xsc2_inten = cpu->cd.arm.r[rd]; |
461 |
|
|
break; |
462 |
|
|
case 5: if (l_bit) |
463 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_flag; |
464 |
|
|
else |
465 |
|
|
cpu->cd.arm.xsc2_flag = cpu->cd.arm.r[rd]; |
466 |
|
|
break; |
467 |
|
|
case 8: if (l_bit) |
468 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_evtsel; |
469 |
|
|
else |
470 |
|
|
cpu->cd.arm.xsc2_evtsel = cpu->cd.arm.r[rd]; |
471 |
|
|
break; |
472 |
|
|
default:goto unknown; |
473 |
|
|
} |
474 |
|
|
break; |
475 |
|
|
|
476 |
|
|
case 2: switch (crn) { |
477 |
|
|
case 0: if (l_bit) |
478 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn0; |
479 |
|
|
else |
480 |
|
|
cpu->cd.arm.xsc2_pmn0 = cpu->cd.arm.r[rd]; |
481 |
|
|
break; |
482 |
|
|
case 1: if (l_bit) |
483 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn1; |
484 |
|
|
else |
485 |
|
|
cpu->cd.arm.xsc2_pmn1 = cpu->cd.arm.r[rd]; |
486 |
|
|
break; |
487 |
|
|
case 2: if (l_bit) |
488 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn2; |
489 |
|
|
else |
490 |
|
|
cpu->cd.arm.xsc2_pmn2 = cpu->cd.arm.r[rd]; |
491 |
|
|
break; |
492 |
|
|
case 3: if (l_bit) |
493 |
|
|
cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn3; |
494 |
|
|
else |
495 |
|
|
cpu->cd.arm.xsc2_pmn3 = cpu->cd.arm.r[rd]; |
496 |
|
|
break; |
497 |
|
|
default:goto unknown; |
498 |
|
|
} |
499 |
|
|
break; |
500 |
|
|
|
501 |
|
|
default:goto unknown; |
502 |
dpavlin |
14 |
} |
503 |
dpavlin |
22 |
|
504 |
|
|
return; |
505 |
|
|
|
506 |
|
|
unknown: |
507 |
|
|
fatal("arm_coproc_xscale_14: unimplemented opcode1=%i opcode2=" |
508 |
|
|
"%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, |
509 |
|
|
crm, rd, l_bit); |
510 |
|
|
exit(1); |
511 |
dpavlin |
14 |
} |
512 |
|
|
|