--- trunk/src/cpus/cpu_arm.c	2007/10/08 16:19:28	21
+++ trunk/src/cpus/cpu_arm.c	2007/10/08 16:19:37	22
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_arm.c,v 1.44 2005/11/19 18:53:07 debug Exp $
+ *  $Id: cpu_arm.c,v 1.54 2006/02/09 20:02:58 debug Exp $
  *
  *  ARM CPU emulation.
  *
@@ -45,6 +45,7 @@
 #include "machine.h"
 #include "memory.h"
 #include "misc.h"
+#include "of.h"
 #include "symbol.h"
 
 #define DYNTRANS_32
@@ -63,7 +64,8 @@
 static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE;
 
 /*  For quick_pc_to_pointers():  */
-#include "arm_quick_pc_to_pointers.h"
+void arm_pc_to_pointers(struct cpu *cpu);
+#include "quick_pc_to_pointers.h"
 
 
 /*
@@ -97,13 +99,14 @@
 	cpu->invalidate_code_translation = arm_invalidate_code_translation;
 	cpu->translate_address = arm_translate_address;
 
-	cpu->cd.arm.cpu_type    = cpu_type_defs[found];
-	cpu->name               = cpu->cd.arm.cpu_type.name;
-	cpu->is_32bit           = 1;
+	cpu->cd.arm.cpu_type = cpu_type_defs[found];
+	cpu->name            = cpu->cd.arm.cpu_type.name;
+	cpu->is_32bit        = 1;
 
 	cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F;
 	cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32
 	    | ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN;
+	/*  TODO: default auxctrl contents  */
 
 	if (cpu->machine->prom_emulation) {
 		cpu->cd.arm.cpsr |= ARM_MODE_SVC32;
@@ -128,9 +131,26 @@
 		}
 	}
 
+	/*  TODO: Some of these values (iway and dway) aren't used yet:  */
+	cpu->cd.arm.cachetype =
+	      (5 << ARM_CACHETYPE_CLASS_SHIFT)
+	    | (1 << ARM_CACHETYPE_HARVARD_SHIFT)
+	    | ((cpu->cd.arm.cpu_type.dcache_shift - 9) <<
+		ARM_CACHETYPE_DSIZE_SHIFT)
+	    | (5 << ARM_CACHETYPE_DASSOC_SHIFT)		/*  32-way  */
+	    | (2 << ARM_CACHETYPE_DLINE_SHIFT)		/*  8 words/line  */
+	    | ((cpu->cd.arm.cpu_type.icache_shift - 9) <<
+		ARM_CACHETYPE_ISIZE_SHIFT)
+	    | (5 << ARM_CACHETYPE_IASSOC_SHIFT)		/*  32-way  */
+	    | (2 << ARM_CACHETYPE_ILINE_SHIFT);		/*  8 words/line  */
+
 	/*  Coprocessor 15 = the system control coprocessor.  */
 	cpu->cd.arm.coproc[15] = arm_coproc_15;
 
+	/*  Coprocessor 14 for XScale:  */
+	if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE)
+		cpu->cd.arm.coproc[14] = arm_coproc_xscale_14;
+
 	/*
 	 *  NOTE/TODO: Ugly hack for OpenFirmware emulation:
 	 */
@@ -301,8 +321,11 @@
 				m->cpus[cpunr]->cd.arm.r[i] = *valuep;
 				if (i == ARM_PC)
 					m->cpus[cpunr]->pc = *valuep;
-			} else
+			} else {
 				*valuep = m->cpus[cpunr]->cd.arm.r[i];
+				if (i == ARM_PC)
+					*valuep = m->cpus[cpunr]->pc;
+			}
 			*match_register = 1;
 		}
 	}
@@ -378,42 +401,42 @@
 		}
 
 		if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) {
-			debug("cpu%i:  usr r8..r14 =", x);
+			debug("cpu%i:  usr r8-14:", x);
 			for (i=0; i<7; i++)
 				debug(" %08x", cpu->cd.arm.default_r8_r14[i]);
 			debug("\n");
 		}
 
 		if (m != ARM_MODE_FIQ32) {
-			debug("cpu%i:  fiq r8..r14 =", x);
+			debug("cpu%i:  fiq r8-14:", x);
 			for (i=0; i<7; i++)
 				debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]);
 			debug("\n");
 		}
 
 		if (m != ARM_MODE_IRQ32) {
-			debug("cpu%i:  irq r13..r14 =", x);
+			debug("cpu%i:  irq r13-14:", x);
 			for (i=0; i<2; i++)
 				debug(" %08x", cpu->cd.arm.irq_r13_r14[i]);
 			debug("\n");
 		}
 
 		if (m != ARM_MODE_SVC32) {
-			debug("cpu%i:  svc r13..r14 =", x);
+			debug("cpu%i:  svc r13-14:", x);
 			for (i=0; i<2; i++)
 				debug(" %08x", cpu->cd.arm.svc_r13_r14[i]);
 			debug("\n");
 		}
 
 		if (m != ARM_MODE_ABT32) {
-			debug("cpu%i:  abt r13..r14 =", x);
+			debug("cpu%i:  abt r13-14:", x);
 			for (i=0; i<2; i++)
 				debug(" %08x", cpu->cd.arm.abt_r13_r14[i]);
 			debug("\n");
 		}
 
 		if (m != ARM_MODE_UND32) {
-			debug("cpu%i:  und r13..r14 =", x);
+			debug("cpu%i:  und r13-14:", x);
 			for (i=0; i<2; i++)
 				debug(" %08x", cpu->cd.arm.und_r13_r14[i]);
 			debug("\n");
@@ -450,6 +473,20 @@
 		    cpu->cd.arm.control &
 		    ARM_CONTROL_V? "yes (0xffff0000)" : "no");
 
+		/*  TODO: auxctrl on which CPU types?  */
+		if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) {
+			debug("cpu%i:  auxctrl = 0x%08x\n", x,
+			    cpu->cd.arm.auxctrl);
+			debug("cpu%i:      minidata cache attr = 0x%x\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)
+			    >> ARM_AUXCTRL_MD_SHIFT);
+			debug("cpu%i:      page table memory attr: %i\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0);
+			debug("cpu%i:      write buffer coalescing: %s\n", x,
+			    (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)?
+			    "disabled" : "enabled");
+		}
+
 		debug("cpu%i:  ttb = 0x%08x  dacr = 0x%08x\n", x,
 		    cpu->cd.arm.ttb, cpu->cd.arm.dacr);
 		debug("cpu%i:  fsr = 0x%08x  far = 0x%08x\n", x,
@@ -652,11 +689,7 @@
 		    "mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc);
 		/*  exit(1);  */
 	}
-#if 0
-if (oldmode==0x10 && newmode ==0x17 && cpu->pc == 0x1644f0)
-single_step = 1;
-/* 00008554 */
-#endif
+
 	cpu->cd.arm.cpsr |= ARM_FLAG_I;
 	if (exception_nr == ARM_EXCEPTION_RESET ||
 	    exception_nr == ARM_EXCEPTION_FIQ)
@@ -696,7 +729,8 @@
 			cpu->machine->md_interrupt(cpu->machine,
 			    cpu, irq_nr, 1);
 		else
-			fatal("arm_cpu_interrupt(): md_interrupt == NULL\n");
+			fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt =="
+			    " NULL\n", (int)irq_nr);
 	} else {
 		/*  Assert ARM IRQs:  */
 		cpu->cd.arm.irq_asserted = 1;
@@ -1229,6 +1263,17 @@
 		 *  xxxx1100 0100nnnn ddddcccc oooommmm    MCRR c,op,Rd,Rn,CRm
 		 *  xxxx1100 0101nnnn ddddcccc oooommmm    MRRC c,op,Rd,Rn,CRm
 		 */
+		if ((iw & 0x0fe00fff) == 0x0c400000) {
+			debug("%s%s\t", iw & 0x100000? "mra" : "mar",
+			    condition);
+			if (iw & 0x100000)
+				debug("%s,%s,acc0\n",
+				    arm_regname[r12], arm_regname[r16]);
+			else
+				debug("acc0,%s,%s\n",
+				    arm_regname[r12], arm_regname[r16]);
+			break;
+		}
 		if ((iw & 0x0fe00000) == 0x0c400000) {
 			debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr",
 			    condition);
@@ -1245,6 +1290,22 @@
 		 *  xxxx1110 oooonnnn ddddpppp qqq0mmmm		CDP
 		 *  xxxx1110 oooLNNNN ddddpppp qqq1MMMM		MRC/MCR
 		 */
+		if ((iw & 0x0ff00ff0) == 0x0e200010) {
+			/*  Special case: mia* DSP instructions  */
+			switch ((iw >> 16) & 0xf) {
+			case  0: debug("mia"); break;
+			case  8: debug("miaph"); break;
+			case 12: debug("miaBB"); break;
+			case 13: debug("miaTB"); break;
+			case 14: debug("miaBT"); break;
+			case 15: debug("miaTT"); break;
+			default: debug("UNKNOWN mia vector instruction?");
+			}
+			debug("%s\t", condition);
+			debug("acc%i,%s,%s\n", ((iw >> 5) & 7),
+			    arm_regname[iw & 15], arm_regname[r12]);
+			break;
+		}
 		if (iw & 0x10) {
 			debug("%s%s\t",
 			    (iw & 0x00100000)? "mrc" : "mcr", condition);