1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.60 2006/06/24 21:47:23 debug Exp $ |
* $Id: cpu_arm.c,v 1.72 2007/06/28 13:36:46 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
39 |
#include <stdlib.h> |
#include <stdlib.h> |
40 |
#include <string.h> |
#include <string.h> |
41 |
#include <ctype.h> |
#include <ctype.h> |
42 |
|
#include <unistd.h> |
43 |
|
|
44 |
#include "arm_cpu_types.h" |
#include "arm_cpu_types.h" |
45 |
#include "cpu.h" |
#include "cpu.h" |
46 |
|
#include "interrupt.h" |
47 |
#include "machine.h" |
#include "machine.h" |
48 |
#include "memory.h" |
#include "memory.h" |
49 |
#include "misc.h" |
#include "misc.h" |
50 |
#include "of.h" |
#include "of.h" |
51 |
|
#include "settings.h" |
52 |
#include "symbol.h" |
#include "symbol.h" |
53 |
|
#include "useremul.h" |
54 |
|
|
55 |
#define DYNTRANS_32 |
#define DYNTRANS_32 |
56 |
#include "tmp_arm_head.c" |
#include "tmp_arm_head.c" |
71 |
void arm_pc_to_pointers(struct cpu *cpu); |
void arm_pc_to_pointers(struct cpu *cpu); |
72 |
#include "quick_pc_to_pointers.h" |
#include "quick_pc_to_pointers.h" |
73 |
|
|
74 |
|
void arm_irq_interrupt_assert(struct interrupt *interrupt); |
75 |
|
void arm_irq_interrupt_deassert(struct interrupt *interrupt); |
76 |
|
|
77 |
|
|
78 |
/* |
/* |
79 |
* arm_cpu_new(): |
* arm_cpu_new(): |
84 |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
85 |
struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
86 |
{ |
{ |
87 |
int any_cache = 0, i, found; |
int i, found; |
88 |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
89 |
|
|
90 |
/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
99 |
if (found == -1) |
if (found == -1) |
100 |
return 0; |
return 0; |
101 |
|
|
102 |
|
cpu->run_instr = arm_run_instr; |
103 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
104 |
cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
105 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
110 |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
111 |
cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
112 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
113 |
|
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
114 |
|
|
115 |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
116 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
128 |
/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
129 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
130 |
debug("%s", cpu->name); |
debug("%s", cpu->name); |
131 |
if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
132 |
any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
133 |
if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
134 |
any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
135 |
if (any_cache) { |
if (isize != 0) |
136 |
debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
137 |
(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
138 |
(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
139 |
debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
140 |
} |
} |
141 |
} |
} |
142 |
|
|
171 |
|
|
172 |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
173 |
|
|
174 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
175 |
|
for (i=0; i<N_ARM_REGS - 1; i++) |
176 |
|
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
177 |
|
|
178 |
|
/* Register the CPU's "IRQ" and "FIQ" interrupts: */ |
179 |
|
{ |
180 |
|
struct interrupt template; |
181 |
|
char name[50]; |
182 |
|
snprintf(name, sizeof(name), "%s.irq", cpu->path); |
183 |
|
|
184 |
|
memset(&template, 0, sizeof(template)); |
185 |
|
template.line = 0; |
186 |
|
template.name = name; |
187 |
|
template.extra = cpu; |
188 |
|
template.interrupt_assert = arm_irq_interrupt_assert; |
189 |
|
template.interrupt_deassert = arm_irq_interrupt_deassert; |
190 |
|
interrupt_handler_register(&template); |
191 |
|
|
192 |
|
/* FIQ: TODO */ |
193 |
|
} |
194 |
|
|
195 |
return 1; |
return 1; |
196 |
} |
} |
197 |
|
|
333 |
|
|
334 |
|
|
335 |
/* |
/* |
|
* arm_cpu_register_match(): |
|
|
*/ |
|
|
void arm_cpu_register_match(struct machine *m, char *name, |
|
|
int writeflag, uint64_t *valuep, int *match_register) |
|
|
{ |
|
|
int i, cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register names: */ |
|
|
for (i=0; i<N_ARM_REGS; i++) { |
|
|
if (strcasecmp(name, arm_regname[i]) == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
|
|
if (i == ARM_PC) |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else { |
|
|
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
|
|
if (i == ARM_PC) |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
} |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
336 |
* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |
337 |
* |
* |
338 |
* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
727 |
} |
} |
728 |
|
|
729 |
|
|
|
static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
|
|
size_t maxlen) |
|
|
{ |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
|
|
value = ((value & 0xff) << 24) + |
|
|
((value & 0xff00) << 8) + |
|
|
((value & 0xff0000) >> 8) + |
|
|
((value & 0xff000000) >> 24); |
|
|
} |
|
|
snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
|
|
} |
|
|
|
|
|
|
|
730 |
/* |
/* |
731 |
* arm_cpu_gdb_stub(): |
* arm_irq_interrupt_assert(): |
732 |
* |
* arm_irq_interrupt_deassert(): |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
|
|
* on success, NULL on failure. |
|
733 |
*/ |
*/ |
734 |
char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
void arm_irq_interrupt_assert(struct interrupt *interrupt) |
735 |
{ |
{ |
736 |
if (strcmp(cmd, "g") == 0) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
737 |
/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
cpu->cd.arm.irq_asserted = 1; |
|
int i; |
|
|
char *r; |
|
|
size_t len = 1 + 18 * sizeof(uint32_t); |
|
|
r = malloc(len); |
|
|
if (r == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
|
r[0] = '\0'; |
|
|
for (i=0; i<15; i++) |
|
|
add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
|
|
add_response_word(cpu, r, cpu->pc, len); |
|
|
/* TODO: fprs: */ |
|
|
for (i=0; i<8; i++) |
|
|
add_response_word(cpu, r, 0, len); |
|
|
/* TODO: fps */ |
|
|
add_response_word(cpu, r, 0, len); |
|
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
|
|
return r; |
|
|
} |
|
|
|
|
|
if (cmd[0] == 'p') { |
|
|
int regnr = strtol(cmd + 1, NULL, 16); |
|
|
size_t len = 2 * sizeof(uint32_t) + 1; |
|
|
char *r = malloc(len); |
|
|
r[0] = '\0'; |
|
|
if (regnr == ARM_PC) { |
|
|
add_response_word(cpu, r, cpu->pc, len); |
|
|
} else if (regnr >= 0 && regnr < ARM_PC) { |
|
|
add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
|
|
} else if (regnr >= 0x10 && regnr <= 0x17) { |
|
|
/* TODO: fprs */ |
|
|
add_response_word(cpu, r, 0, len); |
|
|
add_response_word(cpu, r, 0, len); |
|
|
add_response_word(cpu, r, 0, len); |
|
|
} else if (regnr == 0x18) { |
|
|
/* TODO: fps */ |
|
|
add_response_word(cpu, r, 0, len); |
|
|
} else if (regnr == 0x19) { |
|
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
|
|
} |
|
|
return r; |
|
|
} |
|
|
|
|
|
fatal("arm_cpu_gdb_stub(): TODO\n"); |
|
|
return NULL; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* arm_cpu_interrupt(): |
|
|
* |
|
|
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
|
|
* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
|
|
* |
|
|
* TODO: don't hardcode to footbridge! |
|
|
*/ |
|
|
int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
|
|
{ |
|
|
/* fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
|
|
if (irq_nr <= 64) { |
|
|
if (cpu->machine->md_interrupt != NULL) |
|
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 1); |
|
|
else |
|
|
fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
|
|
" NULL\n", (int)irq_nr); |
|
|
} else { |
|
|
/* Assert ARM IRQs: */ |
|
|
cpu->cd.arm.irq_asserted = 1; |
|
|
} |
|
|
|
|
|
return 1; |
|
738 |
} |
} |
739 |
|
void arm_irq_interrupt_deassert(struct interrupt *interrupt) |
|
|
|
|
/* |
|
|
* arm_cpu_interrupt_ack(): |
|
|
*/ |
|
|
int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
|
740 |
{ |
{ |
741 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
742 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.arm.irq_asserted = 0; |
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 0); |
|
|
} else { |
|
|
/* De-assert ARM IRQs: */ |
|
|
cpu->cd.arm.irq_asserted = 0; |
|
|
} |
|
|
|
|
|
return 1; |
|
743 |
} |
} |
744 |
|
|
745 |
|
|