1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.44 2005/11/19 18:53:07 debug Exp $ |
* $Id: cpu_arm.c,v 1.64 2006/09/09 09:04:32 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
45 |
#include "machine.h" |
#include "machine.h" |
46 |
#include "memory.h" |
#include "memory.h" |
47 |
#include "misc.h" |
#include "misc.h" |
48 |
|
#include "of.h" |
49 |
|
#include "settings.h" |
50 |
#include "symbol.h" |
#include "symbol.h" |
51 |
|
|
52 |
#define DYNTRANS_32 |
#define DYNTRANS_32 |
65 |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
66 |
|
|
67 |
/* For quick_pc_to_pointers(): */ |
/* For quick_pc_to_pointers(): */ |
68 |
#include "arm_quick_pc_to_pointers.h" |
void arm_pc_to_pointers(struct cpu *cpu); |
69 |
|
#include "quick_pc_to_pointers.h" |
70 |
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|
71 |
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|
72 |
/* |
/* |
78 |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
79 |
struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
80 |
{ |
{ |
81 |
int any_cache = 0, i, found; |
int i, found; |
82 |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
83 |
|
|
84 |
/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
93 |
if (found == -1) |
if (found == -1) |
94 |
return 0; |
return 0; |
95 |
|
|
96 |
|
cpu->run_instr = arm_run_instr; |
97 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
98 |
cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
99 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
100 |
arm_invalidate_translation_caches; |
arm_invalidate_translation_caches; |
101 |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
102 |
cpu->translate_address = arm_translate_address; |
cpu->translate_v2p = arm_translate_v2p; |
103 |
|
|
104 |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
105 |
cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
106 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
107 |
|
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
108 |
|
|
109 |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
110 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
111 |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
112 |
|
/* TODO: default auxctrl contents */ |
113 |
|
|
114 |
if (cpu->machine->prom_emulation) { |
if (cpu->machine->prom_emulation) { |
115 |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
122 |
/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
123 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
124 |
debug("%s", cpu->name); |
debug("%s", cpu->name); |
125 |
if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
126 |
any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
127 |
if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
128 |
any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
129 |
if (any_cache) { |
if (isize != 0) |
130 |
debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
131 |
(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
132 |
(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
133 |
debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
134 |
} |
} |
135 |
} |
} |
136 |
|
|
137 |
|
/* TODO: Some of these values (iway and dway) aren't used yet: */ |
138 |
|
cpu->cd.arm.cachetype = |
139 |
|
(5 << ARM_CACHETYPE_CLASS_SHIFT) |
140 |
|
| (1 << ARM_CACHETYPE_HARVARD_SHIFT) |
141 |
|
| ((cpu->cd.arm.cpu_type.dcache_shift - 9) << |
142 |
|
ARM_CACHETYPE_DSIZE_SHIFT) |
143 |
|
| (5 << ARM_CACHETYPE_DASSOC_SHIFT) /* 32-way */ |
144 |
|
| (2 << ARM_CACHETYPE_DLINE_SHIFT) /* 8 words/line */ |
145 |
|
| ((cpu->cd.arm.cpu_type.icache_shift - 9) << |
146 |
|
ARM_CACHETYPE_ISIZE_SHIFT) |
147 |
|
| (5 << ARM_CACHETYPE_IASSOC_SHIFT) /* 32-way */ |
148 |
|
| (2 << ARM_CACHETYPE_ILINE_SHIFT); /* 8 words/line */ |
149 |
|
|
150 |
/* Coprocessor 15 = the system control coprocessor. */ |
/* Coprocessor 15 = the system control coprocessor. */ |
151 |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
152 |
|
|
153 |
|
/* Coprocessor 14 for XScale: */ |
154 |
|
if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) |
155 |
|
cpu->cd.arm.coproc[14] = arm_coproc_xscale_14; |
156 |
|
|
157 |
/* |
/* |
158 |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
159 |
*/ |
*/ |
165 |
|
|
166 |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
167 |
|
|
168 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
169 |
|
for (i=0; i<N_ARM_REGS - 1; i++) |
170 |
|
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
171 |
|
|
172 |
return 1; |
return 1; |
173 |
} |
} |
174 |
|
|
192 |
} |
} |
193 |
|
|
194 |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
195 |
cpu->translate_address = arm_translate_address_mmu; |
cpu->translate_v2p = arm_translate_v2p_mmu; |
196 |
cpu->cd.arm.dacr |= 0x00000003; |
cpu->cd.arm.dacr |= 0x00000003; |
197 |
cpu->cd.arm.ttb = ttb_addr; |
cpu->cd.arm.ttb = ttb_addr; |
198 |
|
|
310 |
|
|
311 |
|
|
312 |
/* |
/* |
|
* arm_cpu_register_match(): |
|
|
*/ |
|
|
void arm_cpu_register_match(struct machine *m, char *name, |
|
|
int writeflag, uint64_t *valuep, int *match_register) |
|
|
{ |
|
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int i, cpunr = 0; |
|
|
|
|
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/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register names: */ |
|
|
for (i=0; i<N_ARM_REGS; i++) { |
|
|
if (strcasecmp(name, arm_regname[i]) == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
|
|
if (i == ARM_PC) |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
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/* |
|
313 |
* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |
314 |
* |
* |
315 |
* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
378 |
} |
} |
379 |
|
|
380 |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
381 |
debug("cpu%i: usr r8..r14 =", x); |
debug("cpu%i: usr r8-14:", x); |
382 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
383 |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
384 |
debug("\n"); |
debug("\n"); |
385 |
} |
} |
386 |
|
|
387 |
if (m != ARM_MODE_FIQ32) { |
if (m != ARM_MODE_FIQ32) { |
388 |
debug("cpu%i: fiq r8..r14 =", x); |
debug("cpu%i: fiq r8-14:", x); |
389 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
390 |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
391 |
debug("\n"); |
debug("\n"); |
392 |
} |
} |
393 |
|
|
394 |
if (m != ARM_MODE_IRQ32) { |
if (m != ARM_MODE_IRQ32) { |
395 |
debug("cpu%i: irq r13..r14 =", x); |
debug("cpu%i: irq r13-14:", x); |
396 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
397 |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
398 |
debug("\n"); |
debug("\n"); |
399 |
} |
} |
400 |
|
|
401 |
if (m != ARM_MODE_SVC32) { |
if (m != ARM_MODE_SVC32) { |
402 |
debug("cpu%i: svc r13..r14 =", x); |
debug("cpu%i: svc r13-14:", x); |
403 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
404 |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
405 |
debug("\n"); |
debug("\n"); |
406 |
} |
} |
407 |
|
|
408 |
if (m != ARM_MODE_ABT32) { |
if (m != ARM_MODE_ABT32) { |
409 |
debug("cpu%i: abt r13..r14 =", x); |
debug("cpu%i: abt r13-14:", x); |
410 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
411 |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
412 |
debug("\n"); |
debug("\n"); |
413 |
} |
} |
414 |
|
|
415 |
if (m != ARM_MODE_UND32) { |
if (m != ARM_MODE_UND32) { |
416 |
debug("cpu%i: und r13..r14 =", x); |
debug("cpu%i: und r13-14:", x); |
417 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
418 |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
419 |
debug("\n"); |
debug("\n"); |
450 |
cpu->cd.arm.control & |
cpu->cd.arm.control & |
451 |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
452 |
|
|
453 |
|
/* TODO: auxctrl on which CPU types? */ |
454 |
|
if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) { |
455 |
|
debug("cpu%i: auxctrl = 0x%08x\n", x, |
456 |
|
cpu->cd.arm.auxctrl); |
457 |
|
debug("cpu%i: minidata cache attr = 0x%x\n", x, |
458 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD) |
459 |
|
>> ARM_AUXCTRL_MD_SHIFT); |
460 |
|
debug("cpu%i: page table memory attr: %i\n", x, |
461 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0); |
462 |
|
debug("cpu%i: write buffer coalescing: %s\n", x, |
463 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)? |
464 |
|
"disabled" : "enabled"); |
465 |
|
} |
466 |
|
|
467 |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
468 |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
469 |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
666 |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
667 |
/* exit(1); */ |
/* exit(1); */ |
668 |
} |
} |
669 |
#if 0 |
|
|
if (oldmode==0x10 && newmode ==0x17 && cpu->pc == 0x1644f0) |
|
|
single_step = 1; |
|
|
/* 00008554 */ |
|
|
#endif |
|
670 |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
671 |
if (exception_nr == ARM_EXCEPTION_RESET || |
if (exception_nr == ARM_EXCEPTION_RESET || |
672 |
exception_nr == ARM_EXCEPTION_FIQ) |
exception_nr == ARM_EXCEPTION_FIQ) |
691 |
|
|
692 |
|
|
693 |
/* |
/* |
694 |
|
* arm_cpu_tlbdump(): |
695 |
|
* |
696 |
|
* Called from the debugger to dump the TLB in a readable format. |
697 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
698 |
|
* |
699 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
700 |
|
* just dumped. |
701 |
|
*/ |
702 |
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
703 |
|
{ |
704 |
|
} |
705 |
|
|
706 |
|
|
707 |
|
static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
708 |
|
size_t maxlen) |
709 |
|
{ |
710 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
711 |
|
value = ((value & 0xff) << 24) + |
712 |
|
((value & 0xff00) << 8) + |
713 |
|
((value & 0xff0000) >> 8) + |
714 |
|
((value & 0xff000000) >> 24); |
715 |
|
} |
716 |
|
snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
717 |
|
} |
718 |
|
|
719 |
|
|
720 |
|
/* |
721 |
|
* arm_cpu_gdb_stub(): |
722 |
|
* |
723 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
724 |
|
* on success, NULL on failure. |
725 |
|
*/ |
726 |
|
char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
727 |
|
{ |
728 |
|
if (strcmp(cmd, "g") == 0) { |
729 |
|
/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
730 |
|
int i; |
731 |
|
char *r; |
732 |
|
size_t len = 1 + 18 * sizeof(uint32_t); |
733 |
|
r = malloc(len); |
734 |
|
if (r == NULL) { |
735 |
|
fprintf(stderr, "out of memory\n"); |
736 |
|
exit(1); |
737 |
|
} |
738 |
|
r[0] = '\0'; |
739 |
|
for (i=0; i<15; i++) |
740 |
|
add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
741 |
|
add_response_word(cpu, r, cpu->pc, len); |
742 |
|
/* TODO: fprs: */ |
743 |
|
for (i=0; i<8; i++) |
744 |
|
add_response_word(cpu, r, 0, len); |
745 |
|
/* TODO: fps */ |
746 |
|
add_response_word(cpu, r, 0, len); |
747 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
748 |
|
return r; |
749 |
|
} |
750 |
|
|
751 |
|
if (cmd[0] == 'p') { |
752 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
753 |
|
size_t len = 2 * sizeof(uint32_t) + 1; |
754 |
|
char *r = malloc(len); |
755 |
|
r[0] = '\0'; |
756 |
|
if (regnr == ARM_PC) { |
757 |
|
add_response_word(cpu, r, cpu->pc, len); |
758 |
|
} else if (regnr >= 0 && regnr < ARM_PC) { |
759 |
|
add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
760 |
|
} else if (regnr >= 0x10 && regnr <= 0x17) { |
761 |
|
/* TODO: fprs */ |
762 |
|
add_response_word(cpu, r, 0, len); |
763 |
|
add_response_word(cpu, r, 0, len); |
764 |
|
add_response_word(cpu, r, 0, len); |
765 |
|
} else if (regnr == 0x18) { |
766 |
|
/* TODO: fps */ |
767 |
|
add_response_word(cpu, r, 0, len); |
768 |
|
} else if (regnr == 0x19) { |
769 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
770 |
|
} |
771 |
|
return r; |
772 |
|
} |
773 |
|
|
774 |
|
fatal("arm_cpu_gdb_stub(): TODO\n"); |
775 |
|
return NULL; |
776 |
|
} |
777 |
|
|
778 |
|
|
779 |
|
/* |
780 |
* arm_cpu_interrupt(): |
* arm_cpu_interrupt(): |
781 |
* |
* |
782 |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
792 |
cpu->machine->md_interrupt(cpu->machine, |
cpu->machine->md_interrupt(cpu->machine, |
793 |
cpu, irq_nr, 1); |
cpu, irq_nr, 1); |
794 |
else |
else |
795 |
fatal("arm_cpu_interrupt(): md_interrupt == NULL\n"); |
fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
796 |
|
" NULL\n", (int)irq_nr); |
797 |
} else { |
} else { |
798 |
/* Assert ARM IRQs: */ |
/* Assert ARM IRQs: */ |
799 |
cpu->cd.arm.irq_asserted = 1; |
cpu->cd.arm.irq_asserted = 1; |
834 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
835 |
*/ |
*/ |
836 |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
837 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
838 |
{ |
{ |
839 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
840 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
1326 |
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
1327 |
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
1328 |
*/ |
*/ |
1329 |
|
if ((iw & 0x0fe00fff) == 0x0c400000) { |
1330 |
|
debug("%s%s\t", iw & 0x100000? "mra" : "mar", |
1331 |
|
condition); |
1332 |
|
if (iw & 0x100000) |
1333 |
|
debug("%s,%s,acc0\n", |
1334 |
|
arm_regname[r12], arm_regname[r16]); |
1335 |
|
else |
1336 |
|
debug("acc0,%s,%s\n", |
1337 |
|
arm_regname[r12], arm_regname[r16]); |
1338 |
|
break; |
1339 |
|
} |
1340 |
if ((iw & 0x0fe00000) == 0x0c400000) { |
if ((iw & 0x0fe00000) == 0x0c400000) { |
1341 |
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
1342 |
condition); |
condition); |
1353 |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
1354 |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
1355 |
*/ |
*/ |
1356 |
|
if ((iw & 0x0ff00ff0) == 0x0e200010) { |
1357 |
|
/* Special case: mia* DSP instructions */ |
1358 |
|
switch ((iw >> 16) & 0xf) { |
1359 |
|
case 0: debug("mia"); break; |
1360 |
|
case 8: debug("miaph"); break; |
1361 |
|
case 12: debug("miaBB"); break; |
1362 |
|
case 13: debug("miaTB"); break; |
1363 |
|
case 14: debug("miaBT"); break; |
1364 |
|
case 15: debug("miaTT"); break; |
1365 |
|
default: debug("UNKNOWN mia vector instruction?"); |
1366 |
|
} |
1367 |
|
debug("%s\t", condition); |
1368 |
|
debug("acc%i,%s,%s\n", ((iw >> 5) & 7), |
1369 |
|
arm_regname[iw & 15], arm_regname[r12]); |
1370 |
|
break; |
1371 |
|
} |
1372 |
if (iw & 0x10) { |
if (iw & 0x10) { |
1373 |
debug("%s%s\t", |
debug("%s%s\t", |
1374 |
(iw & 0x00100000)? "mrc" : "mcr", condition); |
(iw & 0x00100000)? "mrc" : "mcr", condition); |