1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.44 2005/11/19 18:53:07 debug Exp $ |
* $Id: cpu_arm.c,v 1.61 2006/07/16 13:32:26 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
45 |
#include "machine.h" |
#include "machine.h" |
46 |
#include "memory.h" |
#include "memory.h" |
47 |
#include "misc.h" |
#include "misc.h" |
48 |
|
#include "of.h" |
49 |
#include "symbol.h" |
#include "symbol.h" |
50 |
|
|
51 |
#define DYNTRANS_32 |
#define DYNTRANS_32 |
64 |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
65 |
|
|
66 |
/* For quick_pc_to_pointers(): */ |
/* For quick_pc_to_pointers(): */ |
67 |
#include "arm_quick_pc_to_pointers.h" |
void arm_pc_to_pointers(struct cpu *cpu); |
68 |
|
#include "quick_pc_to_pointers.h" |
69 |
|
|
70 |
|
|
71 |
/* |
/* |
92 |
if (found == -1) |
if (found == -1) |
93 |
return 0; |
return 0; |
94 |
|
|
95 |
|
cpu->run_instr = arm_run_instr; |
96 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
97 |
cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
98 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
99 |
arm_invalidate_translation_caches; |
arm_invalidate_translation_caches; |
100 |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
101 |
cpu->translate_address = arm_translate_address; |
cpu->translate_v2p = arm_translate_v2p; |
102 |
|
|
103 |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
104 |
cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
105 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
106 |
|
|
107 |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
108 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
109 |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
110 |
|
/* TODO: default auxctrl contents */ |
111 |
|
|
112 |
if (cpu->machine->prom_emulation) { |
if (cpu->machine->prom_emulation) { |
113 |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
132 |
} |
} |
133 |
} |
} |
134 |
|
|
135 |
|
/* TODO: Some of these values (iway and dway) aren't used yet: */ |
136 |
|
cpu->cd.arm.cachetype = |
137 |
|
(5 << ARM_CACHETYPE_CLASS_SHIFT) |
138 |
|
| (1 << ARM_CACHETYPE_HARVARD_SHIFT) |
139 |
|
| ((cpu->cd.arm.cpu_type.dcache_shift - 9) << |
140 |
|
ARM_CACHETYPE_DSIZE_SHIFT) |
141 |
|
| (5 << ARM_CACHETYPE_DASSOC_SHIFT) /* 32-way */ |
142 |
|
| (2 << ARM_CACHETYPE_DLINE_SHIFT) /* 8 words/line */ |
143 |
|
| ((cpu->cd.arm.cpu_type.icache_shift - 9) << |
144 |
|
ARM_CACHETYPE_ISIZE_SHIFT) |
145 |
|
| (5 << ARM_CACHETYPE_IASSOC_SHIFT) /* 32-way */ |
146 |
|
| (2 << ARM_CACHETYPE_ILINE_SHIFT); /* 8 words/line */ |
147 |
|
|
148 |
/* Coprocessor 15 = the system control coprocessor. */ |
/* Coprocessor 15 = the system control coprocessor. */ |
149 |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
150 |
|
|
151 |
|
/* Coprocessor 14 for XScale: */ |
152 |
|
if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) |
153 |
|
cpu->cd.arm.coproc[14] = arm_coproc_xscale_14; |
154 |
|
|
155 |
/* |
/* |
156 |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
157 |
*/ |
*/ |
186 |
} |
} |
187 |
|
|
188 |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
189 |
cpu->translate_address = arm_translate_address_mmu; |
cpu->translate_v2p = arm_translate_v2p_mmu; |
190 |
cpu->cd.arm.dacr |= 0x00000003; |
cpu->cd.arm.dacr |= 0x00000003; |
191 |
cpu->cd.arm.ttb = ttb_addr; |
cpu->cd.arm.ttb = ttb_addr; |
192 |
|
|
322 |
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
323 |
if (i == ARM_PC) |
if (i == ARM_PC) |
324 |
m->cpus[cpunr]->pc = *valuep; |
m->cpus[cpunr]->pc = *valuep; |
325 |
} else |
} else { |
326 |
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
327 |
|
if (i == ARM_PC) |
328 |
|
*valuep = m->cpus[cpunr]->pc; |
329 |
|
} |
330 |
*match_register = 1; |
*match_register = 1; |
331 |
} |
} |
332 |
} |
} |
402 |
} |
} |
403 |
|
|
404 |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
405 |
debug("cpu%i: usr r8..r14 =", x); |
debug("cpu%i: usr r8-14:", x); |
406 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
407 |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
408 |
debug("\n"); |
debug("\n"); |
409 |
} |
} |
410 |
|
|
411 |
if (m != ARM_MODE_FIQ32) { |
if (m != ARM_MODE_FIQ32) { |
412 |
debug("cpu%i: fiq r8..r14 =", x); |
debug("cpu%i: fiq r8-14:", x); |
413 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
414 |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
415 |
debug("\n"); |
debug("\n"); |
416 |
} |
} |
417 |
|
|
418 |
if (m != ARM_MODE_IRQ32) { |
if (m != ARM_MODE_IRQ32) { |
419 |
debug("cpu%i: irq r13..r14 =", x); |
debug("cpu%i: irq r13-14:", x); |
420 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
421 |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
422 |
debug("\n"); |
debug("\n"); |
423 |
} |
} |
424 |
|
|
425 |
if (m != ARM_MODE_SVC32) { |
if (m != ARM_MODE_SVC32) { |
426 |
debug("cpu%i: svc r13..r14 =", x); |
debug("cpu%i: svc r13-14:", x); |
427 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
428 |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
429 |
debug("\n"); |
debug("\n"); |
430 |
} |
} |
431 |
|
|
432 |
if (m != ARM_MODE_ABT32) { |
if (m != ARM_MODE_ABT32) { |
433 |
debug("cpu%i: abt r13..r14 =", x); |
debug("cpu%i: abt r13-14:", x); |
434 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
435 |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
436 |
debug("\n"); |
debug("\n"); |
437 |
} |
} |
438 |
|
|
439 |
if (m != ARM_MODE_UND32) { |
if (m != ARM_MODE_UND32) { |
440 |
debug("cpu%i: und r13..r14 =", x); |
debug("cpu%i: und r13-14:", x); |
441 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
442 |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
443 |
debug("\n"); |
debug("\n"); |
474 |
cpu->cd.arm.control & |
cpu->cd.arm.control & |
475 |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
476 |
|
|
477 |
|
/* TODO: auxctrl on which CPU types? */ |
478 |
|
if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) { |
479 |
|
debug("cpu%i: auxctrl = 0x%08x\n", x, |
480 |
|
cpu->cd.arm.auxctrl); |
481 |
|
debug("cpu%i: minidata cache attr = 0x%x\n", x, |
482 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD) |
483 |
|
>> ARM_AUXCTRL_MD_SHIFT); |
484 |
|
debug("cpu%i: page table memory attr: %i\n", x, |
485 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0); |
486 |
|
debug("cpu%i: write buffer coalescing: %s\n", x, |
487 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)? |
488 |
|
"disabled" : "enabled"); |
489 |
|
} |
490 |
|
|
491 |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
492 |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
493 |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
690 |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
691 |
/* exit(1); */ |
/* exit(1); */ |
692 |
} |
} |
693 |
#if 0 |
|
|
if (oldmode==0x10 && newmode ==0x17 && cpu->pc == 0x1644f0) |
|
|
single_step = 1; |
|
|
/* 00008554 */ |
|
|
#endif |
|
694 |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
695 |
if (exception_nr == ARM_EXCEPTION_RESET || |
if (exception_nr == ARM_EXCEPTION_RESET || |
696 |
exception_nr == ARM_EXCEPTION_FIQ) |
exception_nr == ARM_EXCEPTION_FIQ) |
715 |
|
|
716 |
|
|
717 |
/* |
/* |
718 |
|
* arm_cpu_tlbdump(): |
719 |
|
* |
720 |
|
* Called from the debugger to dump the TLB in a readable format. |
721 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
722 |
|
* |
723 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
724 |
|
* just dumped. |
725 |
|
*/ |
726 |
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
727 |
|
{ |
728 |
|
} |
729 |
|
|
730 |
|
|
731 |
|
static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
732 |
|
size_t maxlen) |
733 |
|
{ |
734 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
735 |
|
value = ((value & 0xff) << 24) + |
736 |
|
((value & 0xff00) << 8) + |
737 |
|
((value & 0xff0000) >> 8) + |
738 |
|
((value & 0xff000000) >> 24); |
739 |
|
} |
740 |
|
snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
741 |
|
} |
742 |
|
|
743 |
|
|
744 |
|
/* |
745 |
|
* arm_cpu_gdb_stub(): |
746 |
|
* |
747 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
748 |
|
* on success, NULL on failure. |
749 |
|
*/ |
750 |
|
char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
751 |
|
{ |
752 |
|
if (strcmp(cmd, "g") == 0) { |
753 |
|
/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
754 |
|
int i; |
755 |
|
char *r; |
756 |
|
size_t len = 1 + 18 * sizeof(uint32_t); |
757 |
|
r = malloc(len); |
758 |
|
if (r == NULL) { |
759 |
|
fprintf(stderr, "out of memory\n"); |
760 |
|
exit(1); |
761 |
|
} |
762 |
|
r[0] = '\0'; |
763 |
|
for (i=0; i<15; i++) |
764 |
|
add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
765 |
|
add_response_word(cpu, r, cpu->pc, len); |
766 |
|
/* TODO: fprs: */ |
767 |
|
for (i=0; i<8; i++) |
768 |
|
add_response_word(cpu, r, 0, len); |
769 |
|
/* TODO: fps */ |
770 |
|
add_response_word(cpu, r, 0, len); |
771 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
772 |
|
return r; |
773 |
|
} |
774 |
|
|
775 |
|
if (cmd[0] == 'p') { |
776 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
777 |
|
size_t len = 2 * sizeof(uint32_t) + 1; |
778 |
|
char *r = malloc(len); |
779 |
|
r[0] = '\0'; |
780 |
|
if (regnr == ARM_PC) { |
781 |
|
add_response_word(cpu, r, cpu->pc, len); |
782 |
|
} else if (regnr >= 0 && regnr < ARM_PC) { |
783 |
|
add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
784 |
|
} else if (regnr >= 0x10 && regnr <= 0x17) { |
785 |
|
/* TODO: fprs */ |
786 |
|
add_response_word(cpu, r, 0, len); |
787 |
|
add_response_word(cpu, r, 0, len); |
788 |
|
add_response_word(cpu, r, 0, len); |
789 |
|
} else if (regnr == 0x18) { |
790 |
|
/* TODO: fps */ |
791 |
|
add_response_word(cpu, r, 0, len); |
792 |
|
} else if (regnr == 0x19) { |
793 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
794 |
|
} |
795 |
|
return r; |
796 |
|
} |
797 |
|
|
798 |
|
fatal("arm_cpu_gdb_stub(): TODO\n"); |
799 |
|
return NULL; |
800 |
|
} |
801 |
|
|
802 |
|
|
803 |
|
/* |
804 |
* arm_cpu_interrupt(): |
* arm_cpu_interrupt(): |
805 |
* |
* |
806 |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
816 |
cpu->machine->md_interrupt(cpu->machine, |
cpu->machine->md_interrupt(cpu->machine, |
817 |
cpu, irq_nr, 1); |
cpu, irq_nr, 1); |
818 |
else |
else |
819 |
fatal("arm_cpu_interrupt(): md_interrupt == NULL\n"); |
fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
820 |
|
" NULL\n", (int)irq_nr); |
821 |
} else { |
} else { |
822 |
/* Assert ARM IRQs: */ |
/* Assert ARM IRQs: */ |
823 |
cpu->cd.arm.irq_asserted = 1; |
cpu->cd.arm.irq_asserted = 1; |
858 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
859 |
*/ |
*/ |
860 |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
861 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
862 |
{ |
{ |
863 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
864 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
1350 |
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
1351 |
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
1352 |
*/ |
*/ |
1353 |
|
if ((iw & 0x0fe00fff) == 0x0c400000) { |
1354 |
|
debug("%s%s\t", iw & 0x100000? "mra" : "mar", |
1355 |
|
condition); |
1356 |
|
if (iw & 0x100000) |
1357 |
|
debug("%s,%s,acc0\n", |
1358 |
|
arm_regname[r12], arm_regname[r16]); |
1359 |
|
else |
1360 |
|
debug("acc0,%s,%s\n", |
1361 |
|
arm_regname[r12], arm_regname[r16]); |
1362 |
|
break; |
1363 |
|
} |
1364 |
if ((iw & 0x0fe00000) == 0x0c400000) { |
if ((iw & 0x0fe00000) == 0x0c400000) { |
1365 |
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
1366 |
condition); |
condition); |
1377 |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
1378 |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
1379 |
*/ |
*/ |
1380 |
|
if ((iw & 0x0ff00ff0) == 0x0e200010) { |
1381 |
|
/* Special case: mia* DSP instructions */ |
1382 |
|
switch ((iw >> 16) & 0xf) { |
1383 |
|
case 0: debug("mia"); break; |
1384 |
|
case 8: debug("miaph"); break; |
1385 |
|
case 12: debug("miaBB"); break; |
1386 |
|
case 13: debug("miaTB"); break; |
1387 |
|
case 14: debug("miaBT"); break; |
1388 |
|
case 15: debug("miaTT"); break; |
1389 |
|
default: debug("UNKNOWN mia vector instruction?"); |
1390 |
|
} |
1391 |
|
debug("%s\t", condition); |
1392 |
|
debug("acc%i,%s,%s\n", ((iw >> 5) & 7), |
1393 |
|
arm_regname[iw & 15], arm_regname[r12]); |
1394 |
|
break; |
1395 |
|
} |
1396 |
if (iw & 0x10) { |
if (iw & 0x10) { |
1397 |
debug("%s%s\t", |
debug("%s%s\t", |
1398 |
(iw & 0x00100000)? "mrc" : "mcr", condition); |
(iw & 0x00100000)? "mrc" : "mcr", condition); |