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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.c,v 1.64 2006/09/09 09:04:32 debug Exp $ |
* $Id: cpu_arm.c,v 1.71 2007/06/15 00:41:21 debug Exp $ |
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* |
* |
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* ARM CPU emulation. |
* ARM CPU emulation. |
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* |
* |
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#include <stdlib.h> |
#include <stdlib.h> |
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#include <string.h> |
#include <string.h> |
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#include <ctype.h> |
#include <ctype.h> |
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#include <unistd.h> |
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#include "arm_cpu_types.h" |
#include "arm_cpu_types.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "of.h" |
#include "of.h" |
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#include "settings.h" |
#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#include "timer.h" |
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#include "useremul.h" |
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#define DYNTRANS_32 |
#define DYNTRANS_32 |
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#include "tmp_arm_head.c" |
#include "tmp_arm_head.c" |
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extern int native_code_translation_enabled; |
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/* ARM symbolic register names and condition strings: */ |
/* ARM symbolic register names and condition strings: */ |
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static char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES; |
static char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES; |
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static char *arm_condition_string[16] = ARM_CONDITION_STRINGS; |
static char *arm_condition_string[16] = ARM_CONDITION_STRINGS; |
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void arm_pc_to_pointers(struct cpu *cpu); |
void arm_pc_to_pointers(struct cpu *cpu); |
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#include "quick_pc_to_pointers.h" |
#include "quick_pc_to_pointers.h" |
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void arm_irq_interrupt_assert(struct interrupt *interrupt); |
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void arm_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* arm_cpu_new(): |
* arm_cpu_new(): |
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for (i=0; i<N_ARM_REGS - 1; i++) |
for (i=0; i<N_ARM_REGS - 1; i++) |
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CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
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/* Register the CPU's "IRQ" and "FIQ" interrupts: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s.irq", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = arm_irq_interrupt_assert; |
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template.interrupt_deassert = arm_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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/* FIQ: TODO */ |
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} |
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if (native_code_translation_enabled) |
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cpu->sampling_timer = timer_add(CPU_SAMPLE_TIMER_HZ, |
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arm_timer_sample_tick, cpu); |
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return 1; |
return 1; |
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} |
} |
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} |
} |
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static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
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size_t maxlen) |
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{ |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
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value = ((value & 0xff) << 24) + |
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((value & 0xff00) << 8) + |
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((value & 0xff0000) >> 8) + |
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((value & 0xff000000) >> 24); |
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} |
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snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
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} |
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/* |
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* arm_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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if (strcmp(cmd, "g") == 0) { |
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/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
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int i; |
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char *r; |
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size_t len = 1 + 18 * sizeof(uint32_t); |
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r = malloc(len); |
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if (r == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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r[0] = '\0'; |
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for (i=0; i<15; i++) |
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add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
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add_response_word(cpu, r, cpu->pc, len); |
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/* TODO: fprs: */ |
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for (i=0; i<8; i++) |
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add_response_word(cpu, r, 0, len); |
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/* TODO: fps */ |
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add_response_word(cpu, r, 0, len); |
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add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
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return r; |
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} |
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if (cmd[0] == 'p') { |
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int regnr = strtol(cmd + 1, NULL, 16); |
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size_t len = 2 * sizeof(uint32_t) + 1; |
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char *r = malloc(len); |
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r[0] = '\0'; |
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if (regnr == ARM_PC) { |
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add_response_word(cpu, r, cpu->pc, len); |
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} else if (regnr >= 0 && regnr < ARM_PC) { |
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add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
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} else if (regnr >= 0x10 && regnr <= 0x17) { |
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/* TODO: fprs */ |
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add_response_word(cpu, r, 0, len); |
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add_response_word(cpu, r, 0, len); |
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add_response_word(cpu, r, 0, len); |
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} else if (regnr == 0x18) { |
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/* TODO: fps */ |
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add_response_word(cpu, r, 0, len); |
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} else if (regnr == 0x19) { |
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add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
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} |
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return r; |
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} |
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fatal("arm_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
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/* |
/* |
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* arm_cpu_interrupt(): |
* arm_irq_interrupt_assert(): |
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* |
* arm_irq_interrupt_deassert(): |
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* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to footbridge! |
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*/ |
*/ |
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int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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/* fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (irq_nr <= 64) { |
cpu->cd.arm.irq_asserted = 1; |
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if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 1); |
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else |
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fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
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" NULL\n", (int)irq_nr); |
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} else { |
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/* Assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 1; |
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} |
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return 1; |
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} |
} |
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void arm_irq_interrupt_deassert(struct interrupt *interrupt) |
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/* |
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* arm_cpu_interrupt_ack(): |
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*/ |
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int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
{ |
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if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (cpu->machine->md_interrupt != NULL) |
cpu->cd.arm.irq_asserted = 0; |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 0); |
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} else { |
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/* De-assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 0; |
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} |
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return 1; |
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} |
} |
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