/[gxemul]/trunk/src/cpus/cpu_arm.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 38 by dpavlin, Mon Oct 8 16:21:53 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: cpu_arm.c,v 1.54 2006/02/09 20:02:58 debug Exp $   *  $Id: cpu_arm.c,v 1.68 2007/03/26 02:01:35 debug Exp $
29   *   *
30   *  ARM CPU emulation.   *  ARM CPU emulation.
31   *   *
# Line 42  Line 42 
42    
43  #include "arm_cpu_types.h"  #include "arm_cpu_types.h"
44  #include "cpu.h"  #include "cpu.h"
45    #include "interrupt.h"
46  #include "machine.h"  #include "machine.h"
47  #include "memory.h"  #include "memory.h"
48  #include "misc.h"  #include "misc.h"
49  #include "of.h"  #include "of.h"
50    #include "settings.h"
51  #include "symbol.h"  #include "symbol.h"
52    
53  #define DYNTRANS_32  #define DYNTRANS_32
# Line 67  static int arm_exception_to_mode[N_ARM_E Line 69  static int arm_exception_to_mode[N_ARM_E
69  void arm_pc_to_pointers(struct cpu *cpu);  void arm_pc_to_pointers(struct cpu *cpu);
70  #include "quick_pc_to_pointers.h"  #include "quick_pc_to_pointers.h"
71    
72    void arm_irq_interrupt_assert(struct interrupt *interrupt);
73    void arm_irq_interrupt_deassert(struct interrupt *interrupt);
74    
75    
76  /*  /*
77   *  arm_cpu_new():   *  arm_cpu_new():
# Line 77  void arm_pc_to_pointers(struct cpu *cpu) Line 82  void arm_pc_to_pointers(struct cpu *cpu)
82  int arm_cpu_new(struct cpu *cpu, struct memory *mem,  int arm_cpu_new(struct cpu *cpu, struct memory *mem,
83          struct machine *machine, int cpu_id, char *cpu_type_name)          struct machine *machine, int cpu_id, char *cpu_type_name)
84  {  {
85          int any_cache = 0, i, found;          int i, found;
86          struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS;          struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS;
87    
88          /*  Scan the list for this cpu type:  */          /*  Scan the list for this cpu type:  */
# Line 92  int arm_cpu_new(struct cpu *cpu, struct Line 97  int arm_cpu_new(struct cpu *cpu, struct
97          if (found == -1)          if (found == -1)
98                  return 0;                  return 0;
99    
100            cpu->run_instr = arm_run_instr;
101          cpu->memory_rw = arm_memory_rw;          cpu->memory_rw = arm_memory_rw;
102          cpu->update_translation_table = arm_update_translation_table;          cpu->update_translation_table = arm_update_translation_table;
103          cpu->invalidate_translation_caches =          cpu->invalidate_translation_caches =
104              arm_invalidate_translation_caches;              arm_invalidate_translation_caches;
105          cpu->invalidate_code_translation = arm_invalidate_code_translation;          cpu->invalidate_code_translation = arm_invalidate_code_translation;
106          cpu->translate_address = arm_translate_address;          cpu->translate_v2p = arm_translate_v2p;
107    
108          cpu->cd.arm.cpu_type = cpu_type_defs[found];          cpu->cd.arm.cpu_type = cpu_type_defs[found];
109          cpu->name            = cpu->cd.arm.cpu_type.name;          cpu->name            = cpu->cd.arm.cpu_type.name;
110          cpu->is_32bit        = 1;          cpu->is_32bit        = 1;
111            cpu->byte_order      = EMUL_LITTLE_ENDIAN;
112    
113          cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F;          cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F;
114          cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32          cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32
# Line 119  int arm_cpu_new(struct cpu *cpu, struct Line 126  int arm_cpu_new(struct cpu *cpu, struct
126          /*  Only show name and caches etc for CPU nr 0:  */          /*  Only show name and caches etc for CPU nr 0:  */
127          if (cpu_id == 0) {          if (cpu_id == 0) {
128                  debug("%s", cpu->name);                  debug("%s", cpu->name);
129                  if (cpu->cd.arm.cpu_type.icache_shift != 0)                  if (cpu->cd.arm.cpu_type.icache_shift != 0 ||
130                          any_cache = 1;                      cpu->cd.arm.cpu_type.dcache_shift != 0) {
131                  if (cpu->cd.arm.cpu_type.dcache_shift != 0)                          int isize = cpu->cd.arm.cpu_type.icache_shift;
132                          any_cache = 1;                          int dsize = cpu->cd.arm.cpu_type.dcache_shift;
133                  if (any_cache) {                          if (isize != 0)
134                          debug(" (I+D = %i+%i KB",                                  isize = 1 << (isize - 10);
135                              (int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)),                          if (dsize != 0)
136                              (int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10)));                                  dsize = 1 << (dsize - 10);
137                          debug(")");                          debug(" (I+D = %i+%i KB)", isize, dsize);
138                  }                  }
139          }          }
140    
# Line 162  int arm_cpu_new(struct cpu *cpu, struct Line 169  int arm_cpu_new(struct cpu *cpu, struct
169    
170          cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;          cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28;
171    
172            CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
173            for (i=0; i<N_ARM_REGS - 1; i++)
174                    CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]);
175    
176            /*  Register the CPU's "IRQ" and "FIQ" interrupts:  */
177            {
178                    struct interrupt template;
179                    char name[50];
180                    snprintf(name, sizeof(name), "%s.irq", cpu->path);
181    
182                    memset(&template, 0, sizeof(template));
183                    template.line = 0;
184                    template.name = name;
185                    template.extra = cpu;
186                    template.interrupt_assert = arm_irq_interrupt_assert;
187                    template.interrupt_deassert = arm_irq_interrupt_deassert;
188                    interrupt_handler_register(&template);
189    
190                    /*  FIQ: TODO  */
191            }
192    
193    
194          return 1;          return 1;
195  }  }
196    
# Line 185  void arm_setup_initial_translation_table Line 214  void arm_setup_initial_translation_table
214          }          }
215    
216          cpu->cd.arm.control |= ARM_CONTROL_MMU;          cpu->cd.arm.control |= ARM_CONTROL_MMU;
217          cpu->translate_address = arm_translate_address_mmu;          cpu->translate_v2p = arm_translate_v2p_mmu;
218          cpu->cd.arm.dacr |= 0x00000003;          cpu->cd.arm.dacr |= 0x00000003;
219          cpu->cd.arm.ttb = ttb_addr;          cpu->cd.arm.ttb = ttb_addr;
220    
# Line 303  void arm_cpu_list_available_types(void) Line 332  void arm_cpu_list_available_types(void)
332    
333    
334  /*  /*
  *  arm_cpu_register_match():  
  */  
 void arm_cpu_register_match(struct machine *m, char *name,  
         int writeflag, uint64_t *valuep, int *match_register)  
 {  
         int i, cpunr = 0;  
   
         /*  CPU number:  */  
   
         /*  TODO  */  
   
         /*  Register names:  */  
         for (i=0; i<N_ARM_REGS; i++) {  
                 if (strcasecmp(name, arm_regname[i]) == 0) {  
                         if (writeflag) {  
                                 m->cpus[cpunr]->cd.arm.r[i] = *valuep;  
                                 if (i == ARM_PC)  
                                         m->cpus[cpunr]->pc = *valuep;  
                         } else {  
                                 *valuep = m->cpus[cpunr]->cd.arm.r[i];  
                                 if (i == ARM_PC)  
                                         *valuep = m->cpus[cpunr]->pc;  
                         }  
                         *match_register = 1;  
                 }  
         }  
 }  
   
   
 /*  
335   *  arm_cpu_register_dump():   *  arm_cpu_register_dump():
336   *   *
337   *  Dump cpu registers in a relatively readable format.   *  Dump cpu registers in a relatively readable format.
# Line 714  void arm_exception(struct cpu *cpu, int Line 713  void arm_exception(struct cpu *cpu, int
713    
714    
715  /*  /*
716   *  arm_cpu_interrupt():   *  arm_cpu_tlbdump():
717   *   *
718   *  0..31 are used as footbridge interrupt numbers, 32..47 = ISA,   *  Called from the debugger to dump the TLB in a readable format.
719   *  64 is used as a "re-assert" signal to cpu->machine->md_interrupt().   *  x is the cpu number to dump, or -1 to dump all CPUs.
720   *   *
721   *  TODO: don't hardcode to footbridge!   *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
722     *  just dumped.
723   */   */
724  int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)  void arm_cpu_tlbdump(struct machine *m, int x, int rawflag)
725  {  {
         /*  fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr);  */  
         if (irq_nr <= 64) {  
                 if (cpu->machine->md_interrupt != NULL)  
                         cpu->machine->md_interrupt(cpu->machine,  
                             cpu, irq_nr, 1);  
                 else  
                         fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt =="  
                             " NULL\n", (int)irq_nr);  
         } else {  
                 /*  Assert ARM IRQs:  */  
                 cpu->cd.arm.irq_asserted = 1;  
         }  
   
         return 1;  
726  }  }
727    
728    
729  /*  /*
730   *  arm_cpu_interrupt_ack():   *  arm_irq_interrupt_assert():
731     *  arm_irq_interrupt_deassert():
732   */   */
733  int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)  void arm_irq_interrupt_assert(struct interrupt *interrupt)
734  {  {
735          if (irq_nr <= 64) {          struct cpu *cpu = (struct cpu *) interrupt->extra;
736                  if (cpu->machine->md_interrupt != NULL)          cpu->cd.arm.irq_asserted = 1;
737                          cpu->machine->md_interrupt(cpu->machine,  }
738                              cpu, irq_nr, 0);  void arm_irq_interrupt_deassert(struct interrupt *interrupt)
739          } else {  {
740                  /*  De-assert ARM IRQs:  */          struct cpu *cpu = (struct cpu *) interrupt->extra;
741                  cpu->cd.arm.irq_asserted = 0;          cpu->cd.arm.irq_asserted = 0;
         }  
   
         return 1;  
742  }  }
743    
744    
# Line 771  int arm_cpu_interrupt_ack(struct cpu *cp Line 755  int arm_cpu_interrupt_ack(struct cpu *cp
755   *  cpu->pc for relative addresses.   *  cpu->pc for relative addresses.
756   */                       */                    
757  int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,  int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
758          int running, uint64_t dumpaddr, int bintrans)          int running, uint64_t dumpaddr)
759  {  {
760          uint32_t iw, tmp;          uint32_t iw, tmp;
761          int main_opcode, secondary_opcode, s_bit, r16, r12, r8;          int main_opcode, secondary_opcode, s_bit, r16, r12, r8;
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