25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.28 2005/10/07 10:26:03 debug Exp $ |
* $Id: cpu_arm.c,v 1.44 2005/11/19 18:53:07 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
32 |
|
* |
33 |
* A good source of quick info on ARM instruction encoding: |
* A good source of quick info on ARM instruction encoding: |
34 |
* |
* |
35 |
* http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
* http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
|
* |
|
|
* (Most "xxxx0101..." and similar strings in this file are from that URL, |
|
|
* or from the ARM manual.) |
|
36 |
*/ |
*/ |
37 |
|
|
38 |
#include <stdio.h> |
#include <stdio.h> |
60 |
static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
61 |
static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
62 |
|
|
63 |
/* Forward reference: */ |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
64 |
void arm_pc_to_pointers(struct cpu *cpu); |
|
65 |
|
/* For quick_pc_to_pointers(): */ |
66 |
|
#include "arm_quick_pc_to_pointers.h" |
67 |
|
|
68 |
|
|
69 |
/* |
/* |
92 |
|
|
93 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
94 |
cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
95 |
cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
96 |
arm_invalidate_translation_caches_paddr; |
arm_invalidate_translation_caches; |
97 |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
98 |
cpu->translate_address = arm_translate_address; |
cpu->translate_address = arm_translate_address; |
99 |
|
|
109 |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
110 |
cpu->cd.arm.control |= ARM_CONTROL_S; |
cpu->cd.arm.control |= ARM_CONTROL_S; |
111 |
} else { |
} else { |
112 |
cpu->cd.arm.cpsr |= ARM_MODE_USR32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
113 |
cpu->cd.arm.control |= ARM_CONTROL_S | ARM_CONTROL_R; |
cpu->cd.arm.control |= ARM_CONTROL_R; |
114 |
} |
} |
115 |
|
|
116 |
/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
140 |
store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be); |
store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be); |
141 |
} |
} |
142 |
|
|
143 |
|
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
144 |
|
|
145 |
return 1; |
return 1; |
146 |
} |
} |
147 |
|
|
165 |
} |
} |
166 |
|
|
167 |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
168 |
|
cpu->translate_address = arm_translate_address_mmu; |
169 |
cpu->cd.arm.dacr |= 0x00000003; |
cpu->cd.arm.dacr |= 0x00000003; |
170 |
cpu->cd.arm.ttb = ttb_addr; |
cpu->cd.arm.ttb = ttb_addr; |
171 |
|
|
178 |
uint32_t addr = cpu->cd.arm.ttb + |
uint32_t addr = cpu->cd.arm.ttb + |
179 |
(((j << 28) + (i << 20)) >> 18); |
(((j << 28) + (i << 20)) >> 18); |
180 |
uint32_t d = (1048576*i) | 0xc02; |
uint32_t d = (1048576*i) | 0xc02; |
181 |
|
|
182 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
183 |
|
descr[0] = d; descr[1] = d >> 8; |
184 |
|
descr[2] = d >> 16; descr[3] = d >> 24; |
185 |
|
} else { |
186 |
|
descr[3] = d; descr[2] = d >> 8; |
187 |
|
descr[1] = d >> 16; descr[0] = d >> 24; |
188 |
|
} |
189 |
|
cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
190 |
|
sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS); |
191 |
|
} |
192 |
|
} |
193 |
|
|
194 |
|
|
195 |
|
/* |
196 |
|
* arm_translation_table_set_l1(): |
197 |
|
*/ |
198 |
|
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
199 |
|
uint32_t paddr) |
200 |
|
{ |
201 |
|
unsigned int i, j, vhigh = vaddr >> 28, phigh = paddr >> 28; |
202 |
|
|
203 |
|
for (i=0; i<256; i++) |
204 |
|
for (j=vhigh; j<=vhigh; j++) { |
205 |
|
unsigned char descr[4]; |
206 |
|
uint32_t addr = cpu->cd.arm.ttb + |
207 |
|
(((j << 28) + (i << 20)) >> 18); |
208 |
|
uint32_t d = ((phigh << 28) + 1048576*i) | 0xc02; |
209 |
|
|
210 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
211 |
|
descr[0] = d; descr[1] = d >> 8; |
212 |
|
descr[2] = d >> 16; descr[3] = d >> 24; |
213 |
|
} else { |
214 |
|
descr[3] = d; descr[2] = d >> 8; |
215 |
|
descr[1] = d >> 16; descr[0] = d >> 24; |
216 |
|
} |
217 |
|
cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
218 |
|
sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS); |
219 |
|
} |
220 |
|
} |
221 |
|
|
222 |
|
|
223 |
/* |
/* |
224 |
d = (1048576 * (i + (j==12? 10 : j)*256)) | 2; |
* arm_translation_table_set_l1_b(): |
225 |
*/ |
*/ |
226 |
|
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, |
227 |
|
uint32_t paddr) |
228 |
|
{ |
229 |
|
unsigned int i, j, vhigh = vaddr >> 24, phigh = paddr >> 24; |
230 |
|
|
231 |
|
for (i=0; i<16; i++) |
232 |
|
for (j=vhigh; j<=vhigh; j++) { |
233 |
|
unsigned char descr[4]; |
234 |
|
uint32_t addr = cpu->cd.arm.ttb + |
235 |
|
(((j << 24) + (i << 20)) >> 18); |
236 |
|
uint32_t d = ((phigh << 24) + 1048576*i) | 0xc02; |
237 |
|
|
238 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
239 |
descr[0] = d; descr[1] = d >> 8; |
descr[0] = d; descr[1] = d >> 8; |
240 |
descr[2] = d >> 16; descr[3] = d >> 24; |
descr[2] = d >> 16; descr[3] = d >> 24; |
324 |
int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
325 |
int i, x = cpu->cpu_id; |
int i, x = cpu->cpu_id; |
326 |
|
|
327 |
|
cpu->cd.arm.cpsr &= 0x0fffffff; |
328 |
|
cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28); |
329 |
|
|
330 |
if (gprs) { |
if (gprs) { |
331 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
332 |
cpu->cd.arm.r[ARM_PC], &offset); |
cpu->pc, &offset); |
333 |
debug("cpu%i: cpsr = ", x); |
debug("cpu%i: cpsr = ", x); |
334 |
debug("%s%s%s%s%s%s", |
debug("%s%s%s%s%s%s", |
335 |
(cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n", |
(cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n", |
339 |
(cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i", |
(cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i", |
340 |
(cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f"); |
(cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f"); |
341 |
if (mode < ARM_MODE_USR32) |
if (mode < ARM_MODE_USR32) |
342 |
debug(" pc = 0x%07x", |
debug(" pc = 0x%07x", (int)(cpu->pc & 0x03ffffff)); |
|
(int)(cpu->cd.arm.r[ARM_PC] & 0x03ffffff)); |
|
343 |
else |
else |
344 |
debug(" pc = 0x%08x", (int)cpu->cd.arm.r[ARM_PC]); |
debug(" pc = 0x%08x", (int)cpu->pc); |
345 |
|
|
346 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
347 |
|
|
459 |
|
|
460 |
|
|
461 |
/* |
/* |
|
* arm_cpu_show_full_statistics(): |
|
|
* |
|
|
* Show detailed statistics on opcode usage on each cpu. |
|
|
*/ |
|
|
void arm_cpu_show_full_statistics(struct machine *m) |
|
|
{ |
|
|
fatal("arm_cpu_show_full_statistics(): TODO\n"); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* arm_cpu_tlbdump(): |
|
|
* |
|
|
* Called from the debugger to dump the TLB in a readable format. |
|
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
|
|
* |
|
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
|
|
* just dumped. |
|
|
*/ |
|
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
|
{ |
|
|
fatal("arm_cpu_tlbdump(): TODO\n"); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
462 |
* arm_save_register_bank(): |
* arm_save_register_bank(): |
463 |
*/ |
*/ |
464 |
void arm_save_register_bank(struct cpu *cpu) |
void arm_save_register_bank(struct cpu *cpu) |
475 |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 7); |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 7); |
476 |
break; |
break; |
477 |
case ARM_MODE_IRQ32: |
case ARM_MODE_IRQ32: |
478 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
479 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
480 |
cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13]; |
481 |
cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14]; |
482 |
break; |
break; |
483 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
484 |
if ((cpu->cd.arm.r[13] & 0xffff0000) == 0xffff0000) { |
memcpy(cpu->cd.arm.default_r8_r14, |
485 |
fatal("NEJ! pc=0x%08x\n", (int)cpu->pc); |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
|
exit(1); |
|
|
} |
|
486 |
cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13]; |
487 |
cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14]; |
488 |
break; |
break; |
489 |
case ARM_MODE_ABT32: |
case ARM_MODE_ABT32: |
490 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
491 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
492 |
cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13]; |
493 |
cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14]; |
494 |
break; |
break; |
495 |
case ARM_MODE_UND32: |
case ARM_MODE_UND32: |
496 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
497 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
498 |
cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13]; |
499 |
cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14]; |
500 |
break; |
break; |
522 |
sizeof(uint32_t) * 7); |
sizeof(uint32_t) * 7); |
523 |
break; |
break; |
524 |
case ARM_MODE_IRQ32: |
case ARM_MODE_IRQ32: |
525 |
|
memcpy(&cpu->cd.arm.r[8], |
526 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
527 |
cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0]; |
528 |
cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1]; |
529 |
break; |
break; |
530 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
531 |
|
memcpy(&cpu->cd.arm.r[8], |
532 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
533 |
cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0]; |
534 |
cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1]; |
535 |
break; |
break; |
536 |
case ARM_MODE_ABT32: |
case ARM_MODE_ABT32: |
537 |
|
memcpy(&cpu->cd.arm.r[8], |
538 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
539 |
cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0]; |
540 |
cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1]; |
541 |
break; |
break; |
542 |
case ARM_MODE_UND32: |
case ARM_MODE_UND32: |
543 |
|
memcpy(&cpu->cd.arm.r[8], |
544 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
545 |
cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0]; |
546 |
cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1]; |
547 |
break; |
break; |
557 |
*/ |
*/ |
558 |
void arm_exception(struct cpu *cpu, int exception_nr) |
void arm_exception(struct cpu *cpu, int exception_nr) |
559 |
{ |
{ |
|
int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
|
560 |
int oldmode, newmode; |
int oldmode, newmode; |
561 |
uint32_t retaddr; |
uint32_t retaddr; |
562 |
|
|
567 |
|
|
568 |
retaddr = cpu->pc; |
retaddr = cpu->pc; |
569 |
|
|
570 |
debug("[ arm_exception(): "); |
if (!quiet_mode) { |
571 |
|
debug("[ arm_exception(): "); |
572 |
|
switch (exception_nr) { |
573 |
|
case ARM_EXCEPTION_RESET: |
574 |
|
fatal("RESET: TODO"); |
575 |
|
break; |
576 |
|
case ARM_EXCEPTION_UND: |
577 |
|
debug("UNDEFINED"); |
578 |
|
break; |
579 |
|
case ARM_EXCEPTION_SWI: |
580 |
|
debug("SWI"); |
581 |
|
break; |
582 |
|
case ARM_EXCEPTION_PREF_ABT: |
583 |
|
debug("PREFETCH ABORT"); |
584 |
|
break; |
585 |
|
case ARM_EXCEPTION_IRQ: |
586 |
|
debug("IRQ"); |
587 |
|
break; |
588 |
|
case ARM_EXCEPTION_FIQ: |
589 |
|
debug("FIQ"); |
590 |
|
break; |
591 |
|
case ARM_EXCEPTION_DATA_ABT: |
592 |
|
debug("DATA ABORT, far=0x%08x fsr=0x%02x", |
593 |
|
cpu->cd.arm.far, cpu->cd.arm.fsr); |
594 |
|
break; |
595 |
|
} |
596 |
|
debug(" ]\n"); |
597 |
|
} |
598 |
|
|
599 |
switch (exception_nr) { |
switch (exception_nr) { |
600 |
case ARM_EXCEPTION_RESET: |
case ARM_EXCEPTION_RESET: |
601 |
cpu->running = 0; |
cpu->running = 0; |
602 |
fatal("RESET: TODO"); |
fatal("ARM RESET: TODO"); |
603 |
exit(1); |
exit(1); |
|
case ARM_EXCEPTION_UND: |
|
|
debug("UNDEFINED"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_SWI: |
|
|
debug("SWI"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_PREF_ABT: |
|
|
debug("PREFETCH ABORT"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_IRQ: |
|
|
debug("IRQ"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_FIQ: |
|
|
debug("FIQ"); |
|
|
retaddr += 4; |
|
|
break; |
|
604 |
case ARM_EXCEPTION_DATA_ABT: |
case ARM_EXCEPTION_DATA_ABT: |
605 |
debug("DATA ABORT, far=0x%08x fsr=0x%02x", |
retaddr += 4; |
|
cpu->cd.arm.far, cpu->cd.arm.fsr); |
|
|
retaddr += 8; |
|
606 |
break; |
break; |
607 |
} |
} |
608 |
|
|
609 |
debug(" ]\n"); |
retaddr += 4; |
610 |
|
|
611 |
arm_save_register_bank(cpu); |
arm_save_register_bank(cpu); |
612 |
|
|
613 |
|
cpu->cd.arm.cpsr &= 0x0fffffff; |
614 |
|
cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28); |
615 |
|
|
616 |
switch (arm_exception_to_mode[exception_nr]) { |
switch (arm_exception_to_mode[exception_nr]) { |
617 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
618 |
cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break; |
cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break; |
639 |
cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE; |
cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE; |
640 |
cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr]; |
cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr]; |
641 |
|
|
642 |
|
/* |
643 |
|
* Usually, an exception should change modes (so that saved status |
644 |
|
* bits don't get lost). However, Linux on ARM seems to use floating |
645 |
|
* point instructions in the kernel (!), and it emulates those using |
646 |
|
* its own fp emulation code. This leads to a situation where we |
647 |
|
* sometimes change from SVC32 to SVC32. |
648 |
|
*/ |
649 |
newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
650 |
if (oldmode == newmode) { |
if (oldmode == newmode && oldmode != ARM_MODE_SVC32) { |
651 |
fatal("Exception caused no mode change? TODO\n"); |
fatal("[ WARNING! Exception caused no mode change? " |
652 |
exit(1); |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
653 |
|
/* exit(1); */ |
654 |
} |
} |
655 |
|
#if 0 |
656 |
|
if (oldmode==0x10 && newmode ==0x17 && cpu->pc == 0x1644f0) |
657 |
|
single_step = 1; |
658 |
|
/* 00008554 */ |
659 |
|
#endif |
660 |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
661 |
if (exception_nr == ARM_EXCEPTION_RESET || |
if (exception_nr == ARM_EXCEPTION_RESET || |
662 |
exception_nr == ARM_EXCEPTION_FIQ) |
exception_nr == ARM_EXCEPTION_FIQ) |
665 |
/* Load the new register bank, if we switched: */ |
/* Load the new register bank, if we switched: */ |
666 |
arm_load_register_bank(cpu); |
arm_load_register_bank(cpu); |
667 |
|
|
668 |
/* Set the return address and new PC: */ |
/* |
669 |
|
* Set the return address and new PC. |
670 |
|
* |
671 |
|
* NOTE: r[ARM_PC] is also set; see cpu_arm_instr_loadstore.c for |
672 |
|
* details. (If an exception occurs during a load into the pc |
673 |
|
* register, the code in that file assumes that the r[ARM_PC] |
674 |
|
* was changed to the address of the exception handler.) |
675 |
|
*/ |
676 |
cpu->cd.arm.r[ARM_LR] = retaddr; |
cpu->cd.arm.r[ARM_LR] = retaddr; |
|
|
|
677 |
cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 + |
cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 + |
678 |
((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0); |
((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0); |
679 |
arm_pc_to_pointers(cpu); |
quick_pc_to_pointers(cpu); |
680 |
} |
} |
681 |
|
|
682 |
|
|
690 |
*/ |
*/ |
691 |
int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
692 |
{ |
{ |
693 |
/* fatal("arm_cpu_interrupt(): 0x%llx\n", (int)irq_nr); */ |
/* fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
694 |
if (irq_nr <= 64) { |
if (irq_nr <= 64) { |
695 |
if (cpu->machine->md_interrupt != NULL) |
if (cpu->machine->md_interrupt != NULL) |
696 |
cpu->machine->md_interrupt(cpu->machine, |
cpu->machine->md_interrupt(cpu->machine, |
810 |
int a_bit = (iw >> 21) & 1; |
int a_bit = (iw >> 21) & 1; |
811 |
debug("%s%sl%s%s\t", u_bit? "s" : "u", |
debug("%s%sl%s%s\t", u_bit? "s" : "u", |
812 |
a_bit? "mla" : "mul", condition, s_bit? "s" : ""); |
a_bit? "mla" : "mul", condition, s_bit? "s" : ""); |
813 |
debug("%s,", arm_regname[r12]); |
debug("%s,%s,", arm_regname[r12], arm_regname[r16]); |
814 |
debug("%s,", arm_regname[r16]); |
debug("%s,%s\n", arm_regname[iw&15], arm_regname[r8]); |
815 |
debug("%s,", arm_regname[iw & 15]); |
break; |
816 |
debug("%s\n", arm_regname[r8]); |
} |
817 |
|
|
818 |
|
/* |
819 |
|
* xxxx0001 0000nnnn dddd0000 0101mmmm qadd Rd,Rm,Rn |
820 |
|
* xxxx0001 0010nnnn dddd0000 0101mmmm qsub Rd,Rm,Rn |
821 |
|
* xxxx0001 0100nnnn dddd0000 0101mmmm qdadd Rd,Rm,Rn |
822 |
|
* xxxx0001 0110nnnn dddd0000 0101mmmm qdsub Rd,Rm,Rn |
823 |
|
*/ |
824 |
|
if ((iw & 0x0f900ff0) == 0x01000050) { |
825 |
|
debug("q%s%s%s\t", iw & 0x400000? "d" : "", |
826 |
|
iw & 0x200000? "sub" : "add", condition); |
827 |
|
debug("%s,%s,%s\n", arm_regname[r12], |
828 |
|
arm_regname[iw&15], arm_regname[r16]); |
829 |
break; |
break; |
830 |
} |
} |
831 |
|
|
883 |
} |
} |
884 |
|
|
885 |
/* |
/* |
886 |
|
* xxxx0001 01101111 dddd1111 0001mmmm CLZ Rd,Rm |
887 |
|
*/ |
888 |
|
if ((iw & 0x0fff0ff0) == 0x016f0f10) { |
889 |
|
debug("clz%s\t", condition); |
890 |
|
debug("%s,%s\n", arm_regname[r12], arm_regname[iw&15]); |
891 |
|
break; |
892 |
|
} |
893 |
|
|
894 |
|
/* |
895 |
|
* xxxx0001 0000dddd nnnnssss 1yx0mmmm SMLAxy Rd,Rm,Rs,Rn |
896 |
|
* xxxx0001 0100dddd DDDDssss 1yx0mmmm SMLALxy RdL,RdH,Rm,Rs |
897 |
|
* xxxx0001 0010dddd nnnnssss 1y00mmmm SMLAWy Rd,Rm,Rs,Rn |
898 |
|
* xxxx0001 0110dddd 0000ssss 1yx0mmmm SMULxy Rd,Rm,Rs |
899 |
|
* xxxx0001 0010dddd 0000ssss 1y10mmmm SMULWy Rd,Rm,Rs |
900 |
|
*/ |
901 |
|
if ((iw & 0x0ff00090) == 0x01000080) { |
902 |
|
debug("smla%s%s%s\t", |
903 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
904 |
|
condition); |
905 |
|
debug("%s,%s,%s,%s\n", arm_regname[r16], |
906 |
|
arm_regname[iw&15], arm_regname[r8], |
907 |
|
arm_regname[r12]); |
908 |
|
break; |
909 |
|
} |
910 |
|
if ((iw & 0x0ff00090) == 0x01400080) { |
911 |
|
debug("smlal%s%s%s\t", |
912 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
913 |
|
condition); |
914 |
|
debug("%s,%s,%s,%s\n", arm_regname[r12], |
915 |
|
arm_regname[r16], arm_regname[iw&15], |
916 |
|
arm_regname[r8]); |
917 |
|
break; |
918 |
|
} |
919 |
|
if ((iw & 0x0ff000b0) == 0x01200080) { |
920 |
|
debug("smlaw%s%s\t", iw & 0x40? "t" : "b", |
921 |
|
condition); |
922 |
|
debug("%s,%s,%s,%s\n", arm_regname[r16], |
923 |
|
arm_regname[iw&15], arm_regname[r8], |
924 |
|
arm_regname[r12]); |
925 |
|
break; |
926 |
|
} |
927 |
|
if ((iw & 0x0ff0f090) == 0x01600080) { |
928 |
|
debug("smul%s%s%s\t", |
929 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
930 |
|
condition); |
931 |
|
debug("%s,%s,%s\n", arm_regname[r16], |
932 |
|
arm_regname[iw&15], arm_regname[r8]); |
933 |
|
break; |
934 |
|
} |
935 |
|
if ((iw & 0x0ff0f0b0) == 0x012000a0) { |
936 |
|
debug("smulw%s%s\t", iw & 0x40? "t" : "b", |
937 |
|
condition); |
938 |
|
debug("%s,%s,%s\n", arm_regname[r16], |
939 |
|
arm_regname[iw&15], arm_regname[r8]); |
940 |
|
break; |
941 |
|
} |
942 |
|
|
943 |
|
/* |
944 |
* xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn) |
* xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn) |
945 |
*/ |
*/ |
946 |
if ((iw & 0x0e000090) == 0x00000090) { |
if ((iw & 0x0e000090) == 0x00000090) { |
947 |
|
char *op = "st"; |
948 |
int imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
int imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
949 |
int regform = !(iw & 0x00400000); |
int regform = !(iw & 0x00400000); |
950 |
p_bit = main_opcode & 1; |
p_bit = main_opcode & 1; |
957 |
break; |
break; |
958 |
} |
} |
959 |
/* Semi-generic case: */ |
/* Semi-generic case: */ |
960 |
debug("%sr%s", iw & 0x00100000? "ld" : "st", |
if (iw & 0x00100000) |
961 |
condition); |
op = "ld"; |
962 |
|
if (!l_bit && (iw & 0xd0) == 0xd0) |
963 |
|
op = iw & 0x20? "st" : "ld"; |
964 |
|
debug("%sr%s", op, condition); |
965 |
if (!l_bit && (iw & 0xd0) == 0xd0) { |
if (!l_bit && (iw & 0xd0) == 0xd0) { |
966 |
debug("d"); /* Double-register */ |
debug("d"); /* Double-register */ |
967 |
} else { |
} else { |
1161 |
} else { |
} else { |
1162 |
tmpw[0] = addr = cpu->cd.arm.r[r12]; |
tmpw[0] = addr = cpu->cd.arm.r[r12]; |
1163 |
if (r12 == ARM_PC) |
if (r12 == ARM_PC) |
1164 |
addr += 8; |
addr = cpu->pc + 8; |
1165 |
} |
} |
1166 |
debug(": "); |
debug(": "); |
1167 |
if (b_bit) |
if (b_bit) |
1225 |
break; |
break; |
1226 |
case 0xc: /* Coprocessor */ |
case 0xc: /* Coprocessor */ |
1227 |
case 0xd: /* LDC/STC */ |
case 0xd: /* LDC/STC */ |
1228 |
|
/* |
1229 |
|
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
1230 |
|
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
1231 |
|
*/ |
1232 |
|
if ((iw & 0x0fe00000) == 0x0c400000) { |
1233 |
|
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
1234 |
|
condition); |
1235 |
|
debug("%i,%i,%s,%s,cr%i\n", r8, (iw >> 4) & 15, |
1236 |
|
arm_regname[r12], arm_regname[r16], iw & 15); |
1237 |
|
break; |
1238 |
|
} |
1239 |
|
|
1240 |
/* xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC */ |
/* xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC */ |
1241 |
debug("TODO: coprocessor LDC/STC\n"); |
debug("TODO: coprocessor LDC/STC\n"); |
1242 |
break; |
break; |
1301 |
cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit, |
cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit, |
1302 |
crn, crm, rd); |
crn, crm, rd); |
1303 |
else { |
else { |
1304 |
fatal("arm_mcr_mrc: pc=0x%08x, iword=0x%08x: " |
fatal("[ arm_mcr_mrc: pc=0x%08x, iword=0x%08x: " |
1305 |
"cp_num=%i\n", (int)cpu->pc, iword, cp_num); |
"cp_num=%i ]\n", (int)cpu->pc, iword, cp_num); |
1306 |
exit(1); |
arm_exception(cpu, ARM_EXCEPTION_UND); |
1307 |
|
/* exit(1); */ |
1308 |
} |
} |
1309 |
} |
} |
1310 |
|
|
1319 |
*/ |
*/ |
1320 |
void arm_cdp(struct cpu *cpu, uint32_t iword) |
void arm_cdp(struct cpu *cpu, uint32_t iword) |
1321 |
{ |
{ |
1322 |
fatal("arm_cdp: pc=0x%08x, iword=0x%08x\n", (int)cpu->pc, iword); |
fatal("[ arm_cdp: pc=0x%08x, iword=0x%08x ]\n", (int)cpu->pc, iword); |
1323 |
exit(1); |
arm_exception(cpu, ARM_EXCEPTION_UND); |
1324 |
|
/* exit(1); */ |
1325 |
} |
} |
1326 |
|
|
1327 |
|
|