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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.c,v 1.28 2005/10/07 10:26:03 debug Exp $ |
* $Id: cpu_arm.c,v 1.72 2007/06/28 13:36:46 debug Exp $ |
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* |
* |
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* ARM CPU emulation. |
* ARM CPU emulation. |
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* |
* |
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* |
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* A good source of quick info on ARM instruction encoding: |
* A good source of quick info on ARM instruction encoding: |
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* |
* |
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* http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
* http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
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* |
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* (Most "xxxx0101..." and similar strings in this file are from that URL, |
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* or from the ARM manual.) |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include <stdlib.h> |
#include <stdlib.h> |
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#include <string.h> |
#include <string.h> |
41 |
#include <ctype.h> |
#include <ctype.h> |
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#include <unistd.h> |
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#include "arm_cpu_types.h" |
#include "arm_cpu_types.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "of.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#include "useremul.h" |
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#define DYNTRANS_32 |
#define DYNTRANS_32 |
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#include "tmp_arm_head.c" |
#include "tmp_arm_head.c" |
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static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
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static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
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/* Forward reference: */ |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
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/* For quick_pc_to_pointers(): */ |
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void arm_pc_to_pointers(struct cpu *cpu); |
void arm_pc_to_pointers(struct cpu *cpu); |
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#include "quick_pc_to_pointers.h" |
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void arm_irq_interrupt_assert(struct interrupt *interrupt); |
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void arm_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
{ |
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int any_cache = 0, i, found; |
int i, found; |
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struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
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/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
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if (found == -1) |
if (found == -1) |
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return 0; |
return 0; |
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cpu->run_instr = arm_run_instr; |
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cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
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cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
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arm_invalidate_translation_caches_paddr; |
arm_invalidate_translation_caches; |
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cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
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cpu->translate_address = arm_translate_address; |
cpu->translate_v2p = arm_translate_v2p; |
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cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
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cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
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cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
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| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
118 |
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/* TODO: default auxctrl contents */ |
119 |
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if (cpu->machine->prom_emulation) { |
if (cpu->machine->prom_emulation) { |
121 |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
122 |
cpu->cd.arm.control |= ARM_CONTROL_S; |
cpu->cd.arm.control |= ARM_CONTROL_S; |
123 |
} else { |
} else { |
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cpu->cd.arm.cpsr |= ARM_MODE_USR32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
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cpu->cd.arm.control |= ARM_CONTROL_S | ARM_CONTROL_R; |
cpu->cd.arm.control |= ARM_CONTROL_R; |
126 |
} |
} |
127 |
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/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
129 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
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debug("%s", cpu->name); |
debug("%s", cpu->name); |
131 |
if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
132 |
any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
133 |
if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
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any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
135 |
if (any_cache) { |
if (isize != 0) |
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debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
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(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
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(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
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debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
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} |
} |
141 |
} |
} |
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/* TODO: Some of these values (iway and dway) aren't used yet: */ |
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cpu->cd.arm.cachetype = |
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(5 << ARM_CACHETYPE_CLASS_SHIFT) |
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| (1 << ARM_CACHETYPE_HARVARD_SHIFT) |
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| ((cpu->cd.arm.cpu_type.dcache_shift - 9) << |
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ARM_CACHETYPE_DSIZE_SHIFT) |
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| (5 << ARM_CACHETYPE_DASSOC_SHIFT) /* 32-way */ |
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| (2 << ARM_CACHETYPE_DLINE_SHIFT) /* 8 words/line */ |
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| ((cpu->cd.arm.cpu_type.icache_shift - 9) << |
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ARM_CACHETYPE_ISIZE_SHIFT) |
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| (5 << ARM_CACHETYPE_IASSOC_SHIFT) /* 32-way */ |
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| (2 << ARM_CACHETYPE_ILINE_SHIFT); /* 8 words/line */ |
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/* Coprocessor 15 = the system control coprocessor. */ |
/* Coprocessor 15 = the system control coprocessor. */ |
157 |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
158 |
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/* Coprocessor 14 for XScale: */ |
160 |
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if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) |
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cpu->cd.arm.coproc[14] = arm_coproc_xscale_14; |
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/* |
/* |
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* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
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*/ |
*/ |
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store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be); |
store_32bit_word(cpu, cpu->cd.arm.of_emul_addr, 0xef8c64be); |
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} |
} |
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cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_ARM_REGS - 1; i++) |
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CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
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/* Register the CPU's "IRQ" and "FIQ" interrupts: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s.irq", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = arm_irq_interrupt_assert; |
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template.interrupt_deassert = arm_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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/* FIQ: TODO */ |
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} |
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return 1; |
return 1; |
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} |
} |
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} |
} |
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cpu->cd.arm.control |= ARM_CONTROL_MMU; |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
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cpu->translate_v2p = arm_translate_v2p_mmu; |
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cpu->cd.arm.dacr |= 0x00000003; |
cpu->cd.arm.dacr |= 0x00000003; |
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cpu->cd.arm.ttb = ttb_addr; |
cpu->cd.arm.ttb = ttb_addr; |
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uint32_t addr = cpu->cd.arm.ttb + |
uint32_t addr = cpu->cd.arm.ttb + |
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(((j << 28) + (i << 20)) >> 18); |
(((j << 28) + (i << 20)) >> 18); |
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uint32_t d = (1048576*i) | 0xc02; |
uint32_t d = (1048576*i) | 0xc02; |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
233 |
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descr[0] = d; descr[1] = d >> 8; |
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descr[2] = d >> 16; descr[3] = d >> 24; |
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} else { |
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descr[3] = d; descr[2] = d >> 8; |
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descr[1] = d >> 16; descr[0] = d >> 24; |
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} |
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cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
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sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS); |
241 |
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} |
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} |
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/* |
/* |
246 |
d = (1048576 * (i + (j==12? 10 : j)*256)) | 2; |
* arm_translation_table_set_l1(): |
247 |
*/ |
*/ |
248 |
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void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
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uint32_t paddr) |
250 |
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{ |
251 |
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unsigned int i, j, vhigh = vaddr >> 28, phigh = paddr >> 28; |
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253 |
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for (i=0; i<256; i++) |
254 |
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for (j=vhigh; j<=vhigh; j++) { |
255 |
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unsigned char descr[4]; |
256 |
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uint32_t addr = cpu->cd.arm.ttb + |
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(((j << 28) + (i << 20)) >> 18); |
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uint32_t d = ((phigh << 28) + 1048576*i) | 0xc02; |
259 |
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260 |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
261 |
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descr[0] = d; descr[1] = d >> 8; |
262 |
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descr[2] = d >> 16; descr[3] = d >> 24; |
263 |
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} else { |
264 |
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descr[3] = d; descr[2] = d >> 8; |
265 |
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descr[1] = d >> 16; descr[0] = d >> 24; |
266 |
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} |
267 |
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cpu->memory_rw(cpu, cpu->mem, addr, &descr[0], |
268 |
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sizeof(descr), MEM_WRITE, PHYSICAL | NO_EXCEPTIONS); |
269 |
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} |
270 |
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} |
271 |
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272 |
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273 |
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/* |
274 |
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* arm_translation_table_set_l1_b(): |
275 |
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*/ |
276 |
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void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, |
277 |
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uint32_t paddr) |
278 |
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{ |
279 |
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unsigned int i, j, vhigh = vaddr >> 24, phigh = paddr >> 24; |
280 |
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281 |
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for (i=0; i<16; i++) |
282 |
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for (j=vhigh; j<=vhigh; j++) { |
283 |
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unsigned char descr[4]; |
284 |
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uint32_t addr = cpu->cd.arm.ttb + |
285 |
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(((j << 24) + (i << 20)) >> 18); |
286 |
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uint32_t d = ((phigh << 24) + 1048576*i) | 0xc02; |
287 |
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|
288 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
289 |
descr[0] = d; descr[1] = d >> 8; |
descr[0] = d; descr[1] = d >> 8; |
290 |
descr[2] = d >> 16; descr[3] = d >> 24; |
descr[2] = d >> 16; descr[3] = d >> 24; |
333 |
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334 |
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335 |
/* |
/* |
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* arm_cpu_register_match(): |
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*/ |
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void arm_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register names: */ |
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for (i=0; i<N_ARM_REGS; i++) { |
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if (strcasecmp(name, arm_regname[i]) == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
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if (i == ARM_PC) |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
|
336 |
* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |
337 |
* |
* |
338 |
* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
347 |
int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
int mode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
348 |
int i, x = cpu->cpu_id; |
int i, x = cpu->cpu_id; |
349 |
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|
350 |
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cpu->cd.arm.cpsr &= 0x0fffffff; |
351 |
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cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28); |
352 |
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|
353 |
if (gprs) { |
if (gprs) { |
354 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
355 |
cpu->cd.arm.r[ARM_PC], &offset); |
cpu->pc, &offset); |
356 |
debug("cpu%i: cpsr = ", x); |
debug("cpu%i: cpsr = ", x); |
357 |
debug("%s%s%s%s%s%s", |
debug("%s%s%s%s%s%s", |
358 |
(cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n", |
(cpu->cd.arm.cpsr & ARM_FLAG_N)? "N" : "n", |
362 |
(cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i", |
(cpu->cd.arm.cpsr & ARM_FLAG_I)? "I" : "i", |
363 |
(cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f"); |
(cpu->cd.arm.cpsr & ARM_FLAG_F)? "F" : "f"); |
364 |
if (mode < ARM_MODE_USR32) |
if (mode < ARM_MODE_USR32) |
365 |
debug(" pc = 0x%07x", |
debug(" pc = 0x%07x", (int)(cpu->pc & 0x03ffffff)); |
|
(int)(cpu->cd.arm.r[ARM_PC] & 0x03ffffff)); |
|
366 |
else |
else |
367 |
debug(" pc = 0x%08x", (int)cpu->cd.arm.r[ARM_PC]); |
debug(" pc = 0x%08x", (int)cpu->pc); |
368 |
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|
369 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
370 |
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|
401 |
} |
} |
402 |
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|
403 |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
404 |
debug("cpu%i: usr r8..r14 =", x); |
debug("cpu%i: usr r8-14:", x); |
405 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
406 |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
407 |
debug("\n"); |
debug("\n"); |
408 |
} |
} |
409 |
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|
410 |
if (m != ARM_MODE_FIQ32) { |
if (m != ARM_MODE_FIQ32) { |
411 |
debug("cpu%i: fiq r8..r14 =", x); |
debug("cpu%i: fiq r8-14:", x); |
412 |
for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
413 |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
414 |
debug("\n"); |
debug("\n"); |
415 |
} |
} |
416 |
|
|
417 |
if (m != ARM_MODE_IRQ32) { |
if (m != ARM_MODE_IRQ32) { |
418 |
debug("cpu%i: irq r13..r14 =", x); |
debug("cpu%i: irq r13-14:", x); |
419 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
420 |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
421 |
debug("\n"); |
debug("\n"); |
422 |
} |
} |
423 |
|
|
424 |
if (m != ARM_MODE_SVC32) { |
if (m != ARM_MODE_SVC32) { |
425 |
debug("cpu%i: svc r13..r14 =", x); |
debug("cpu%i: svc r13-14:", x); |
426 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
427 |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
428 |
debug("\n"); |
debug("\n"); |
429 |
} |
} |
430 |
|
|
431 |
if (m != ARM_MODE_ABT32) { |
if (m != ARM_MODE_ABT32) { |
432 |
debug("cpu%i: abt r13..r14 =", x); |
debug("cpu%i: abt r13-14:", x); |
433 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
434 |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
435 |
debug("\n"); |
debug("\n"); |
436 |
} |
} |
437 |
|
|
438 |
if (m != ARM_MODE_UND32) { |
if (m != ARM_MODE_UND32) { |
439 |
debug("cpu%i: und r13..r14 =", x); |
debug("cpu%i: und r13-14:", x); |
440 |
for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
441 |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
442 |
debug("\n"); |
debug("\n"); |
473 |
cpu->cd.arm.control & |
cpu->cd.arm.control & |
474 |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
475 |
|
|
476 |
|
/* TODO: auxctrl on which CPU types? */ |
477 |
|
if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) { |
478 |
|
debug("cpu%i: auxctrl = 0x%08x\n", x, |
479 |
|
cpu->cd.arm.auxctrl); |
480 |
|
debug("cpu%i: minidata cache attr = 0x%x\n", x, |
481 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD) |
482 |
|
>> ARM_AUXCTRL_MD_SHIFT); |
483 |
|
debug("cpu%i: page table memory attr: %i\n", x, |
484 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0); |
485 |
|
debug("cpu%i: write buffer coalescing: %s\n", x, |
486 |
|
(cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)? |
487 |
|
"disabled" : "enabled"); |
488 |
|
} |
489 |
|
|
490 |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
491 |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
492 |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
496 |
|
|
497 |
|
|
498 |
/* |
/* |
|
* arm_cpu_show_full_statistics(): |
|
|
* |
|
|
* Show detailed statistics on opcode usage on each cpu. |
|
|
*/ |
|
|
void arm_cpu_show_full_statistics(struct machine *m) |
|
|
{ |
|
|
fatal("arm_cpu_show_full_statistics(): TODO\n"); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* arm_cpu_tlbdump(): |
|
|
* |
|
|
* Called from the debugger to dump the TLB in a readable format. |
|
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
|
|
* |
|
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
|
|
* just dumped. |
|
|
*/ |
|
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
|
{ |
|
|
fatal("arm_cpu_tlbdump(): TODO\n"); |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
499 |
* arm_save_register_bank(): |
* arm_save_register_bank(): |
500 |
*/ |
*/ |
501 |
void arm_save_register_bank(struct cpu *cpu) |
void arm_save_register_bank(struct cpu *cpu) |
512 |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 7); |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 7); |
513 |
break; |
break; |
514 |
case ARM_MODE_IRQ32: |
case ARM_MODE_IRQ32: |
515 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
516 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
517 |
cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.irq_r13_r14[0] = cpu->cd.arm.r[13]; |
518 |
cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.irq_r13_r14[1] = cpu->cd.arm.r[14]; |
519 |
break; |
break; |
520 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
521 |
if ((cpu->cd.arm.r[13] & 0xffff0000) == 0xffff0000) { |
memcpy(cpu->cd.arm.default_r8_r14, |
522 |
fatal("NEJ! pc=0x%08x\n", (int)cpu->pc); |
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
|
exit(1); |
|
|
} |
|
523 |
cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.svc_r13_r14[0] = cpu->cd.arm.r[13]; |
524 |
cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.svc_r13_r14[1] = cpu->cd.arm.r[14]; |
525 |
break; |
break; |
526 |
case ARM_MODE_ABT32: |
case ARM_MODE_ABT32: |
527 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
528 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
529 |
cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.abt_r13_r14[0] = cpu->cd.arm.r[13]; |
530 |
cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.abt_r13_r14[1] = cpu->cd.arm.r[14]; |
531 |
break; |
break; |
532 |
case ARM_MODE_UND32: |
case ARM_MODE_UND32: |
533 |
|
memcpy(cpu->cd.arm.default_r8_r14, |
534 |
|
&cpu->cd.arm.r[8], sizeof(uint32_t) * 5); |
535 |
cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13]; |
cpu->cd.arm.und_r13_r14[0] = cpu->cd.arm.r[13]; |
536 |
cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14]; |
cpu->cd.arm.und_r13_r14[1] = cpu->cd.arm.r[14]; |
537 |
break; |
break; |
559 |
sizeof(uint32_t) * 7); |
sizeof(uint32_t) * 7); |
560 |
break; |
break; |
561 |
case ARM_MODE_IRQ32: |
case ARM_MODE_IRQ32: |
562 |
|
memcpy(&cpu->cd.arm.r[8], |
563 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
564 |
cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.irq_r13_r14[0]; |
565 |
cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.irq_r13_r14[1]; |
566 |
break; |
break; |
567 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
568 |
|
memcpy(&cpu->cd.arm.r[8], |
569 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
570 |
cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.svc_r13_r14[0]; |
571 |
cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.svc_r13_r14[1]; |
572 |
break; |
break; |
573 |
case ARM_MODE_ABT32: |
case ARM_MODE_ABT32: |
574 |
|
memcpy(&cpu->cd.arm.r[8], |
575 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
576 |
cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.abt_r13_r14[0]; |
577 |
cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.abt_r13_r14[1]; |
578 |
break; |
break; |
579 |
case ARM_MODE_UND32: |
case ARM_MODE_UND32: |
580 |
|
memcpy(&cpu->cd.arm.r[8], |
581 |
|
cpu->cd.arm.default_r8_r14, sizeof(uint32_t) * 5); |
582 |
cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0]; |
cpu->cd.arm.r[13] = cpu->cd.arm.und_r13_r14[0]; |
583 |
cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1]; |
cpu->cd.arm.r[14] = cpu->cd.arm.und_r13_r14[1]; |
584 |
break; |
break; |
594 |
*/ |
*/ |
595 |
void arm_exception(struct cpu *cpu, int exception_nr) |
void arm_exception(struct cpu *cpu, int exception_nr) |
596 |
{ |
{ |
|
int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
|
597 |
int oldmode, newmode; |
int oldmode, newmode; |
598 |
uint32_t retaddr; |
uint32_t retaddr; |
599 |
|
|
604 |
|
|
605 |
retaddr = cpu->pc; |
retaddr = cpu->pc; |
606 |
|
|
607 |
debug("[ arm_exception(): "); |
if (!quiet_mode) { |
608 |
|
debug("[ arm_exception(): "); |
609 |
|
switch (exception_nr) { |
610 |
|
case ARM_EXCEPTION_RESET: |
611 |
|
fatal("RESET: TODO"); |
612 |
|
break; |
613 |
|
case ARM_EXCEPTION_UND: |
614 |
|
debug("UNDEFINED"); |
615 |
|
break; |
616 |
|
case ARM_EXCEPTION_SWI: |
617 |
|
debug("SWI"); |
618 |
|
break; |
619 |
|
case ARM_EXCEPTION_PREF_ABT: |
620 |
|
debug("PREFETCH ABORT"); |
621 |
|
break; |
622 |
|
case ARM_EXCEPTION_IRQ: |
623 |
|
debug("IRQ"); |
624 |
|
break; |
625 |
|
case ARM_EXCEPTION_FIQ: |
626 |
|
debug("FIQ"); |
627 |
|
break; |
628 |
|
case ARM_EXCEPTION_DATA_ABT: |
629 |
|
debug("DATA ABORT, far=0x%08x fsr=0x%02x", |
630 |
|
cpu->cd.arm.far, cpu->cd.arm.fsr); |
631 |
|
break; |
632 |
|
} |
633 |
|
debug(" ]\n"); |
634 |
|
} |
635 |
|
|
636 |
switch (exception_nr) { |
switch (exception_nr) { |
637 |
case ARM_EXCEPTION_RESET: |
case ARM_EXCEPTION_RESET: |
638 |
cpu->running = 0; |
cpu->running = 0; |
639 |
fatal("RESET: TODO"); |
fatal("ARM RESET: TODO"); |
640 |
exit(1); |
exit(1); |
|
case ARM_EXCEPTION_UND: |
|
|
debug("UNDEFINED"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_SWI: |
|
|
debug("SWI"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_PREF_ABT: |
|
|
debug("PREFETCH ABORT"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_IRQ: |
|
|
debug("IRQ"); |
|
|
retaddr += 4; |
|
|
break; |
|
|
case ARM_EXCEPTION_FIQ: |
|
|
debug("FIQ"); |
|
|
retaddr += 4; |
|
|
break; |
|
641 |
case ARM_EXCEPTION_DATA_ABT: |
case ARM_EXCEPTION_DATA_ABT: |
642 |
debug("DATA ABORT, far=0x%08x fsr=0x%02x", |
retaddr += 4; |
|
cpu->cd.arm.far, cpu->cd.arm.fsr); |
|
|
retaddr += 8; |
|
643 |
break; |
break; |
644 |
} |
} |
645 |
|
|
646 |
debug(" ]\n"); |
retaddr += 4; |
647 |
|
|
648 |
arm_save_register_bank(cpu); |
arm_save_register_bank(cpu); |
649 |
|
|
650 |
|
cpu->cd.arm.cpsr &= 0x0fffffff; |
651 |
|
cpu->cd.arm.cpsr |= (cpu->cd.arm.flags << 28); |
652 |
|
|
653 |
switch (arm_exception_to_mode[exception_nr]) { |
switch (arm_exception_to_mode[exception_nr]) { |
654 |
case ARM_MODE_SVC32: |
case ARM_MODE_SVC32: |
655 |
cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break; |
cpu->cd.arm.spsr_svc = cpu->cd.arm.cpsr; break; |
676 |
cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE; |
cpu->cd.arm.cpsr &= ~ARM_FLAG_MODE; |
677 |
cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr]; |
cpu->cd.arm.cpsr |= arm_exception_to_mode[exception_nr]; |
678 |
|
|
679 |
|
/* |
680 |
|
* Usually, an exception should change modes (so that saved status |
681 |
|
* bits don't get lost). However, Linux on ARM seems to use floating |
682 |
|
* point instructions in the kernel (!), and it emulates those using |
683 |
|
* its own fp emulation code. This leads to a situation where we |
684 |
|
* sometimes change from SVC32 to SVC32. |
685 |
|
*/ |
686 |
newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
newmode = cpu->cd.arm.cpsr & ARM_FLAG_MODE; |
687 |
if (oldmode == newmode) { |
if (oldmode == newmode && oldmode != ARM_MODE_SVC32) { |
688 |
fatal("Exception caused no mode change? TODO\n"); |
fatal("[ WARNING! Exception caused no mode change? " |
689 |
exit(1); |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
690 |
|
/* exit(1); */ |
691 |
} |
} |
692 |
|
|
693 |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
698 |
/* Load the new register bank, if we switched: */ |
/* Load the new register bank, if we switched: */ |
699 |
arm_load_register_bank(cpu); |
arm_load_register_bank(cpu); |
700 |
|
|
701 |
/* Set the return address and new PC: */ |
/* |
702 |
|
* Set the return address and new PC. |
703 |
|
* |
704 |
|
* NOTE: r[ARM_PC] is also set; see cpu_arm_instr_loadstore.c for |
705 |
|
* details. (If an exception occurs during a load into the pc |
706 |
|
* register, the code in that file assumes that the r[ARM_PC] |
707 |
|
* was changed to the address of the exception handler.) |
708 |
|
*/ |
709 |
cpu->cd.arm.r[ARM_LR] = retaddr; |
cpu->cd.arm.r[ARM_LR] = retaddr; |
|
|
|
710 |
cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 + |
cpu->pc = cpu->cd.arm.r[ARM_PC] = exception_nr * 4 + |
711 |
((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0); |
((cpu->cd.arm.control & ARM_CONTROL_V)? 0xffff0000 : 0); |
712 |
arm_pc_to_pointers(cpu); |
quick_pc_to_pointers(cpu); |
713 |
} |
} |
714 |
|
|
715 |
|
|
716 |
/* |
/* |
717 |
* arm_cpu_interrupt(): |
* arm_cpu_tlbdump(): |
718 |
* |
* |
719 |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
* Called from the debugger to dump the TLB in a readable format. |
720 |
* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
* x is the cpu number to dump, or -1 to dump all CPUs. |
721 |
* |
* |
722 |
* TODO: don't hardcode to footbridge! |
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
723 |
|
* just dumped. |
724 |
*/ |
*/ |
725 |
int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
726 |
{ |
{ |
|
/* fatal("arm_cpu_interrupt(): 0x%llx\n", (int)irq_nr); */ |
|
|
if (irq_nr <= 64) { |
|
|
if (cpu->machine->md_interrupt != NULL) |
|
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 1); |
|
|
else |
|
|
fatal("arm_cpu_interrupt(): md_interrupt == NULL\n"); |
|
|
} else { |
|
|
/* Assert ARM IRQs: */ |
|
|
cpu->cd.arm.irq_asserted = 1; |
|
|
} |
|
|
|
|
|
return 1; |
|
727 |
} |
} |
728 |
|
|
729 |
|
|
730 |
/* |
/* |
731 |
* arm_cpu_interrupt_ack(): |
* arm_irq_interrupt_assert(): |
732 |
|
* arm_irq_interrupt_deassert(): |
733 |
*/ |
*/ |
734 |
int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_assert(struct interrupt *interrupt) |
735 |
{ |
{ |
736 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
737 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.arm.irq_asserted = 1; |
738 |
cpu->machine->md_interrupt(cpu->machine, |
} |
739 |
cpu, irq_nr, 0); |
void arm_irq_interrupt_deassert(struct interrupt *interrupt) |
740 |
} else { |
{ |
741 |
/* De-assert ARM IRQs: */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
742 |
cpu->cd.arm.irq_asserted = 0; |
cpu->cd.arm.irq_asserted = 0; |
|
} |
|
|
|
|
|
return 1; |
|
743 |
} |
} |
744 |
|
|
745 |
|
|
756 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
757 |
*/ |
*/ |
758 |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
759 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
760 |
{ |
{ |
761 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
762 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
829 |
int a_bit = (iw >> 21) & 1; |
int a_bit = (iw >> 21) & 1; |
830 |
debug("%s%sl%s%s\t", u_bit? "s" : "u", |
debug("%s%sl%s%s\t", u_bit? "s" : "u", |
831 |
a_bit? "mla" : "mul", condition, s_bit? "s" : ""); |
a_bit? "mla" : "mul", condition, s_bit? "s" : ""); |
832 |
debug("%s,", arm_regname[r12]); |
debug("%s,%s,", arm_regname[r12], arm_regname[r16]); |
833 |
debug("%s,", arm_regname[r16]); |
debug("%s,%s\n", arm_regname[iw&15], arm_regname[r8]); |
834 |
debug("%s,", arm_regname[iw & 15]); |
break; |
835 |
debug("%s\n", arm_regname[r8]); |
} |
836 |
|
|
837 |
|
/* |
838 |
|
* xxxx0001 0000nnnn dddd0000 0101mmmm qadd Rd,Rm,Rn |
839 |
|
* xxxx0001 0010nnnn dddd0000 0101mmmm qsub Rd,Rm,Rn |
840 |
|
* xxxx0001 0100nnnn dddd0000 0101mmmm qdadd Rd,Rm,Rn |
841 |
|
* xxxx0001 0110nnnn dddd0000 0101mmmm qdsub Rd,Rm,Rn |
842 |
|
*/ |
843 |
|
if ((iw & 0x0f900ff0) == 0x01000050) { |
844 |
|
debug("q%s%s%s\t", iw & 0x400000? "d" : "", |
845 |
|
iw & 0x200000? "sub" : "add", condition); |
846 |
|
debug("%s,%s,%s\n", arm_regname[r12], |
847 |
|
arm_regname[iw&15], arm_regname[r16]); |
848 |
break; |
break; |
849 |
} |
} |
850 |
|
|
902 |
} |
} |
903 |
|
|
904 |
/* |
/* |
905 |
|
* xxxx0001 01101111 dddd1111 0001mmmm CLZ Rd,Rm |
906 |
|
*/ |
907 |
|
if ((iw & 0x0fff0ff0) == 0x016f0f10) { |
908 |
|
debug("clz%s\t", condition); |
909 |
|
debug("%s,%s\n", arm_regname[r12], arm_regname[iw&15]); |
910 |
|
break; |
911 |
|
} |
912 |
|
|
913 |
|
/* |
914 |
|
* xxxx0001 0000dddd nnnnssss 1yx0mmmm SMLAxy Rd,Rm,Rs,Rn |
915 |
|
* xxxx0001 0100dddd DDDDssss 1yx0mmmm SMLALxy RdL,RdH,Rm,Rs |
916 |
|
* xxxx0001 0010dddd nnnnssss 1y00mmmm SMLAWy Rd,Rm,Rs,Rn |
917 |
|
* xxxx0001 0110dddd 0000ssss 1yx0mmmm SMULxy Rd,Rm,Rs |
918 |
|
* xxxx0001 0010dddd 0000ssss 1y10mmmm SMULWy Rd,Rm,Rs |
919 |
|
*/ |
920 |
|
if ((iw & 0x0ff00090) == 0x01000080) { |
921 |
|
debug("smla%s%s%s\t", |
922 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
923 |
|
condition); |
924 |
|
debug("%s,%s,%s,%s\n", arm_regname[r16], |
925 |
|
arm_regname[iw&15], arm_regname[r8], |
926 |
|
arm_regname[r12]); |
927 |
|
break; |
928 |
|
} |
929 |
|
if ((iw & 0x0ff00090) == 0x01400080) { |
930 |
|
debug("smlal%s%s%s\t", |
931 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
932 |
|
condition); |
933 |
|
debug("%s,%s,%s,%s\n", arm_regname[r12], |
934 |
|
arm_regname[r16], arm_regname[iw&15], |
935 |
|
arm_regname[r8]); |
936 |
|
break; |
937 |
|
} |
938 |
|
if ((iw & 0x0ff000b0) == 0x01200080) { |
939 |
|
debug("smlaw%s%s\t", iw & 0x40? "t" : "b", |
940 |
|
condition); |
941 |
|
debug("%s,%s,%s,%s\n", arm_regname[r16], |
942 |
|
arm_regname[iw&15], arm_regname[r8], |
943 |
|
arm_regname[r12]); |
944 |
|
break; |
945 |
|
} |
946 |
|
if ((iw & 0x0ff0f090) == 0x01600080) { |
947 |
|
debug("smul%s%s%s\t", |
948 |
|
iw & 0x20? "t" : "b", iw & 0x40? "t" : "b", |
949 |
|
condition); |
950 |
|
debug("%s,%s,%s\n", arm_regname[r16], |
951 |
|
arm_regname[iw&15], arm_regname[r8]); |
952 |
|
break; |
953 |
|
} |
954 |
|
if ((iw & 0x0ff0f0b0) == 0x012000a0) { |
955 |
|
debug("smulw%s%s\t", iw & 0x40? "t" : "b", |
956 |
|
condition); |
957 |
|
debug("%s,%s,%s\n", arm_regname[r16], |
958 |
|
arm_regname[iw&15], arm_regname[r8]); |
959 |
|
break; |
960 |
|
} |
961 |
|
|
962 |
|
/* |
963 |
* xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn) |
* xxxx000P U1WLnnnn ddddHHHH 1SH1LLLL load/store rd,imm(rn) |
964 |
*/ |
*/ |
965 |
if ((iw & 0x0e000090) == 0x00000090) { |
if ((iw & 0x0e000090) == 0x00000090) { |
966 |
|
char *op = "st"; |
967 |
int imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
int imm = ((iw >> 4) & 0xf0) | (iw & 0xf); |
968 |
int regform = !(iw & 0x00400000); |
int regform = !(iw & 0x00400000); |
969 |
p_bit = main_opcode & 1; |
p_bit = main_opcode & 1; |
976 |
break; |
break; |
977 |
} |
} |
978 |
/* Semi-generic case: */ |
/* Semi-generic case: */ |
979 |
debug("%sr%s", iw & 0x00100000? "ld" : "st", |
if (iw & 0x00100000) |
980 |
condition); |
op = "ld"; |
981 |
|
if (!l_bit && (iw & 0xd0) == 0xd0) |
982 |
|
op = iw & 0x20? "st" : "ld"; |
983 |
|
debug("%sr%s", op, condition); |
984 |
if (!l_bit && (iw & 0xd0) == 0xd0) { |
if (!l_bit && (iw & 0xd0) == 0xd0) { |
985 |
debug("d"); /* Double-register */ |
debug("d"); /* Double-register */ |
986 |
} else { |
} else { |
1180 |
} else { |
} else { |
1181 |
tmpw[0] = addr = cpu->cd.arm.r[r12]; |
tmpw[0] = addr = cpu->cd.arm.r[r12]; |
1182 |
if (r12 == ARM_PC) |
if (r12 == ARM_PC) |
1183 |
addr += 8; |
addr = cpu->pc + 8; |
1184 |
} |
} |
1185 |
debug(": "); |
debug(": "); |
1186 |
if (b_bit) |
if (b_bit) |
1244 |
break; |
break; |
1245 |
case 0xc: /* Coprocessor */ |
case 0xc: /* Coprocessor */ |
1246 |
case 0xd: /* LDC/STC */ |
case 0xd: /* LDC/STC */ |
1247 |
|
/* |
1248 |
|
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
1249 |
|
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
1250 |
|
*/ |
1251 |
|
if ((iw & 0x0fe00fff) == 0x0c400000) { |
1252 |
|
debug("%s%s\t", iw & 0x100000? "mra" : "mar", |
1253 |
|
condition); |
1254 |
|
if (iw & 0x100000) |
1255 |
|
debug("%s,%s,acc0\n", |
1256 |
|
arm_regname[r12], arm_regname[r16]); |
1257 |
|
else |
1258 |
|
debug("acc0,%s,%s\n", |
1259 |
|
arm_regname[r12], arm_regname[r16]); |
1260 |
|
break; |
1261 |
|
} |
1262 |
|
if ((iw & 0x0fe00000) == 0x0c400000) { |
1263 |
|
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
1264 |
|
condition); |
1265 |
|
debug("%i,%i,%s,%s,cr%i\n", r8, (iw >> 4) & 15, |
1266 |
|
arm_regname[r12], arm_regname[r16], iw & 15); |
1267 |
|
break; |
1268 |
|
} |
1269 |
|
|
1270 |
/* xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC */ |
/* xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC */ |
1271 |
debug("TODO: coprocessor LDC/STC\n"); |
debug("TODO: coprocessor LDC/STC\n"); |
1272 |
break; |
break; |
1275 |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
1276 |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
1277 |
*/ |
*/ |
1278 |
|
if ((iw & 0x0ff00ff0) == 0x0e200010) { |
1279 |
|
/* Special case: mia* DSP instructions */ |
1280 |
|
switch ((iw >> 16) & 0xf) { |
1281 |
|
case 0: debug("mia"); break; |
1282 |
|
case 8: debug("miaph"); break; |
1283 |
|
case 12: debug("miaBB"); break; |
1284 |
|
case 13: debug("miaTB"); break; |
1285 |
|
case 14: debug("miaBT"); break; |
1286 |
|
case 15: debug("miaTT"); break; |
1287 |
|
default: debug("UNKNOWN mia vector instruction?"); |
1288 |
|
} |
1289 |
|
debug("%s\t", condition); |
1290 |
|
debug("acc%i,%s,%s\n", ((iw >> 5) & 7), |
1291 |
|
arm_regname[iw & 15], arm_regname[r12]); |
1292 |
|
break; |
1293 |
|
} |
1294 |
if (iw & 0x10) { |
if (iw & 0x10) { |
1295 |
debug("%s%s\t", |
debug("%s%s\t", |
1296 |
(iw & 0x00100000)? "mrc" : "mcr", condition); |
(iw & 0x00100000)? "mrc" : "mcr", condition); |
1347 |
cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit, |
cpu->cd.arm.coproc[cp_num](cpu, opcode1, opcode2, l_bit, |
1348 |
crn, crm, rd); |
crn, crm, rd); |
1349 |
else { |
else { |
1350 |
fatal("arm_mcr_mrc: pc=0x%08x, iword=0x%08x: " |
fatal("[ arm_mcr_mrc: pc=0x%08x, iword=0x%08x: " |
1351 |
"cp_num=%i\n", (int)cpu->pc, iword, cp_num); |
"cp_num=%i ]\n", (int)cpu->pc, iword, cp_num); |
1352 |
exit(1); |
arm_exception(cpu, ARM_EXCEPTION_UND); |
1353 |
|
/* exit(1); */ |
1354 |
} |
} |
1355 |
} |
} |
1356 |
|
|
1365 |
*/ |
*/ |
1366 |
void arm_cdp(struct cpu *cpu, uint32_t iword) |
void arm_cdp(struct cpu *cpu, uint32_t iword) |
1367 |
{ |
{ |
1368 |
fatal("arm_cdp: pc=0x%08x, iword=0x%08x\n", (int)cpu->pc, iword); |
fatal("[ arm_cdp: pc=0x%08x, iword=0x%08x ]\n", (int)cpu->pc, iword); |
1369 |
exit(1); |
arm_exception(cpu, ARM_EXCEPTION_UND); |
1370 |
|
/* exit(1); */ |
1371 |
} |
} |
1372 |
|
|
1373 |
|
|