25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.54 2006/02/09 20:02:58 debug Exp $ |
* $Id: cpu_arm.c,v 1.64 2006/09/09 09:04:32 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
46 |
#include "memory.h" |
#include "memory.h" |
47 |
#include "misc.h" |
#include "misc.h" |
48 |
#include "of.h" |
#include "of.h" |
49 |
|
#include "settings.h" |
50 |
#include "symbol.h" |
#include "symbol.h" |
51 |
|
|
52 |
#define DYNTRANS_32 |
#define DYNTRANS_32 |
78 |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
79 |
struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
80 |
{ |
{ |
81 |
int any_cache = 0, i, found; |
int i, found; |
82 |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
83 |
|
|
84 |
/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
93 |
if (found == -1) |
if (found == -1) |
94 |
return 0; |
return 0; |
95 |
|
|
96 |
|
cpu->run_instr = arm_run_instr; |
97 |
cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
98 |
cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
99 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
100 |
arm_invalidate_translation_caches; |
arm_invalidate_translation_caches; |
101 |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
102 |
cpu->translate_address = arm_translate_address; |
cpu->translate_v2p = arm_translate_v2p; |
103 |
|
|
104 |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
105 |
cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
106 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
107 |
|
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
108 |
|
|
109 |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
110 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
122 |
/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
123 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
124 |
debug("%s", cpu->name); |
debug("%s", cpu->name); |
125 |
if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
126 |
any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
127 |
if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
128 |
any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
129 |
if (any_cache) { |
if (isize != 0) |
130 |
debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
131 |
(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
132 |
(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
133 |
debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
134 |
} |
} |
135 |
} |
} |
136 |
|
|
165 |
|
|
166 |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
167 |
|
|
168 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
169 |
|
for (i=0; i<N_ARM_REGS - 1; i++) |
170 |
|
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
171 |
|
|
172 |
return 1; |
return 1; |
173 |
} |
} |
174 |
|
|
192 |
} |
} |
193 |
|
|
194 |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
cpu->cd.arm.control |= ARM_CONTROL_MMU; |
195 |
cpu->translate_address = arm_translate_address_mmu; |
cpu->translate_v2p = arm_translate_v2p_mmu; |
196 |
cpu->cd.arm.dacr |= 0x00000003; |
cpu->cd.arm.dacr |= 0x00000003; |
197 |
cpu->cd.arm.ttb = ttb_addr; |
cpu->cd.arm.ttb = ttb_addr; |
198 |
|
|
310 |
|
|
311 |
|
|
312 |
/* |
/* |
|
* arm_cpu_register_match(): |
|
|
*/ |
|
|
void arm_cpu_register_match(struct machine *m, char *name, |
|
|
int writeflag, uint64_t *valuep, int *match_register) |
|
|
{ |
|
|
int i, cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register names: */ |
|
|
for (i=0; i<N_ARM_REGS; i++) { |
|
|
if (strcasecmp(name, arm_regname[i]) == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
|
|
if (i == ARM_PC) |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else { |
|
|
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
|
|
if (i == ARM_PC) |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
} |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
313 |
* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |
314 |
* |
* |
315 |
* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
691 |
|
|
692 |
|
|
693 |
/* |
/* |
694 |
|
* arm_cpu_tlbdump(): |
695 |
|
* |
696 |
|
* Called from the debugger to dump the TLB in a readable format. |
697 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
698 |
|
* |
699 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
700 |
|
* just dumped. |
701 |
|
*/ |
702 |
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
703 |
|
{ |
704 |
|
} |
705 |
|
|
706 |
|
|
707 |
|
static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
708 |
|
size_t maxlen) |
709 |
|
{ |
710 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
711 |
|
value = ((value & 0xff) << 24) + |
712 |
|
((value & 0xff00) << 8) + |
713 |
|
((value & 0xff0000) >> 8) + |
714 |
|
((value & 0xff000000) >> 24); |
715 |
|
} |
716 |
|
snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
717 |
|
} |
718 |
|
|
719 |
|
|
720 |
|
/* |
721 |
|
* arm_cpu_gdb_stub(): |
722 |
|
* |
723 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
724 |
|
* on success, NULL on failure. |
725 |
|
*/ |
726 |
|
char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
727 |
|
{ |
728 |
|
if (strcmp(cmd, "g") == 0) { |
729 |
|
/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
730 |
|
int i; |
731 |
|
char *r; |
732 |
|
size_t len = 1 + 18 * sizeof(uint32_t); |
733 |
|
r = malloc(len); |
734 |
|
if (r == NULL) { |
735 |
|
fprintf(stderr, "out of memory\n"); |
736 |
|
exit(1); |
737 |
|
} |
738 |
|
r[0] = '\0'; |
739 |
|
for (i=0; i<15; i++) |
740 |
|
add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
741 |
|
add_response_word(cpu, r, cpu->pc, len); |
742 |
|
/* TODO: fprs: */ |
743 |
|
for (i=0; i<8; i++) |
744 |
|
add_response_word(cpu, r, 0, len); |
745 |
|
/* TODO: fps */ |
746 |
|
add_response_word(cpu, r, 0, len); |
747 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
748 |
|
return r; |
749 |
|
} |
750 |
|
|
751 |
|
if (cmd[0] == 'p') { |
752 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
753 |
|
size_t len = 2 * sizeof(uint32_t) + 1; |
754 |
|
char *r = malloc(len); |
755 |
|
r[0] = '\0'; |
756 |
|
if (regnr == ARM_PC) { |
757 |
|
add_response_word(cpu, r, cpu->pc, len); |
758 |
|
} else if (regnr >= 0 && regnr < ARM_PC) { |
759 |
|
add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
760 |
|
} else if (regnr >= 0x10 && regnr <= 0x17) { |
761 |
|
/* TODO: fprs */ |
762 |
|
add_response_word(cpu, r, 0, len); |
763 |
|
add_response_word(cpu, r, 0, len); |
764 |
|
add_response_word(cpu, r, 0, len); |
765 |
|
} else if (regnr == 0x18) { |
766 |
|
/* TODO: fps */ |
767 |
|
add_response_word(cpu, r, 0, len); |
768 |
|
} else if (regnr == 0x19) { |
769 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
770 |
|
} |
771 |
|
return r; |
772 |
|
} |
773 |
|
|
774 |
|
fatal("arm_cpu_gdb_stub(): TODO\n"); |
775 |
|
return NULL; |
776 |
|
} |
777 |
|
|
778 |
|
|
779 |
|
/* |
780 |
* arm_cpu_interrupt(): |
* arm_cpu_interrupt(): |
781 |
* |
* |
782 |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
834 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
835 |
*/ |
*/ |
836 |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
837 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
838 |
{ |
{ |
839 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
840 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |