/[gxemul]/trunk/src/cpus/cpu_alpha_palcode.c
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Annotation of /trunk/src/cpus/cpu_alpha_palcode.c

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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 10172 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: cpu_alpha_palcode.c,v 1.16 2006/12/30 13:30:53 debug Exp $
29 dpavlin 14 *
30     * Alpha PALcode-related functionality.
31 dpavlin 32 *
32     * (See http://www.alphalinux.org/docs/alphaahb.html for good descriptions
33     * of many PALcode functions.)
34 dpavlin 14 */
35    
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40     #include <ctype.h>
41    
42     #include "misc.h"
43    
44    
45     #ifndef ENABLE_ALPHA
46    
47    
48     #include "cpu_alpha.h"
49    
50    
51     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
52     { buf[0]='\0'; }
53     void alpha_palcode(struct cpu *cpu, uint32_t palcode) { }
54    
55    
56     #else /* ENABLE_ALPHA */
57    
58    
59 dpavlin 32 #include "alpha_prom.h"
60 dpavlin 14 #include "console.h"
61     #include "cpu.h"
62     #include "machine.h"
63     #include "memory.h"
64     #include "symbol.h"
65    
66    
67     /*
68     * alpha_palcode_name():
69     *
70     * Return the name of a PALcode number, as a string.
71     */
72     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
73     {
74     switch (palcode) {
75     case 0x10: snprintf(buf, buflen, "PAL_OSF1_rdmces"); break;
76     case 0x11: snprintf(buf, buflen, "PAL_OSF1_wrmces"); break;
77     case 0x2b: snprintf(buf, buflen, "PAL_OSF1_wrfen"); break;
78     case 0x2d: snprintf(buf, buflen, "PAL_OSF1_wrvptptr"); break;
79     case 0x30: snprintf(buf, buflen, "PAL_OSF1_swpctx"); break;
80     case 0x31: snprintf(buf, buflen, "PAL_OSF1_wrval"); break;
81     case 0x32: snprintf(buf, buflen, "PAL_OSF1_rdval"); break;
82     case 0x33: snprintf(buf, buflen, "PAL_OSF1_tbi"); break;
83     case 0x34: snprintf(buf, buflen, "PAL_OSF1_wrent"); break;
84     case 0x35: snprintf(buf, buflen, "PAL_OSF1_swpipl"); break;
85     case 0x36: snprintf(buf, buflen, "PAL_OSF1_rdps"); break;
86     case 0x37: snprintf(buf, buflen, "PAL_OSF1_wrkgp"); break;
87     case 0x38: snprintf(buf, buflen, "PAL_OSF1_wrusp"); break;
88     case 0x39: snprintf(buf, buflen, "PAL_OSF1_wrperfmon"); break;
89     case 0x3a: snprintf(buf, buflen, "PAL_OSF1_rdusp"); break;
90     case 0x3c: snprintf(buf, buflen, "PAL_OSF1_whami"); break;
91     case 0x3d: snprintf(buf, buflen, "PAL_OSF1_retsys"); break;
92     case 0x3f: snprintf(buf, buflen, "PAL_OSF1_rti"); break;
93 dpavlin 22 case 0x81: snprintf(buf, buflen, "PAL_bugchk"); break;
94 dpavlin 14 case 0x83: snprintf(buf, buflen, "PAL_OSF1_callsys"); break;
95     case 0x86: snprintf(buf, buflen, "PAL_OSF1_imb"); break;
96     case 0x92: snprintf(buf, buflen, "PAL_OSF1_urti"); break;
97     case 0x3fffffe: snprintf(buf, buflen, "GXemul_PROM"); break;
98 dpavlin 32 default:snprintf(buf, buflen, "UNKNOWN 0x%"PRIx32, palcode);
99 dpavlin 14 }
100     }
101    
102    
103     /*
104     * alpha_prom_call():
105     */
106     void alpha_prom_call(struct cpu *cpu)
107     {
108 dpavlin 32 uint64_t addr, a1 = cpu->cd.alpha.r[ALPHA_A1];
109     uint64_t a2 = cpu->cd.alpha.r[ALPHA_A2], a3 = cpu->cd.alpha.r[ALPHA_A3];
110     uint64_t len;
111     char *s = "";
112 dpavlin 14
113     switch (cpu->cd.alpha.r[ALPHA_A0]) {
114 dpavlin 32
115     case PROM_R_PUTS:
116     /* a1 = channel, a2 = ptr to buf, a3 = len */
117     for (addr = a2; addr < a2 + a3; addr ++) {
118 dpavlin 14 unsigned char ch;
119     cpu->memory_rw(cpu, cpu->mem, addr, &ch, sizeof(ch),
120     MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
121     console_putchar(cpu->machine->main_console_handle, ch);
122     }
123 dpavlin 32 cpu->cd.alpha.r[ALPHA_V0] = a3;
124 dpavlin 14 break;
125 dpavlin 32
126     case PROM_R_GETENV:
127     /* a1 = variable id, a2 = char *buf, a3 = bufsize */
128     switch (a1) {
129     case PROM_E_BOOTED_DEV:
130     s = ""; /* TODO */
131     break;
132     case PROM_E_BOOTED_FILE:
133     s = cpu->machine->boot_kernel_filename;
134     break;
135     case PROM_E_BOOTED_OSFLAGS:
136     s = cpu->machine->boot_string_argument;
137     break;
138     case PROM_E_TTY_DEV:
139     s = ""; /* TODO */
140     break;
141     default:fatal("[ Alpha PALcode: GXemul PROM getenv %i: TODO "
142     "]\n", cpu->cd.alpha.r[ALPHA_A1]);
143     cpu->running = 0;
144     }
145     /* Copy at most a3 bytes. */
146     len = a3;
147     if (strlen(s) < len)
148     len = strlen(s) + 1;
149     store_buf(cpu, a2, s, len);
150 dpavlin 14 break;
151 dpavlin 32
152 dpavlin 24 default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%"PRIx64" ]\n",
153     (uint64_t) cpu->cd.alpha.r[ALPHA_A0]);
154 dpavlin 14 cpu->running = 0;
155     }
156    
157     /* Return from the PROM call. */
158     cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
159     }
160    
161    
162     /*
163     * alpha_palcode():
164     *
165     * Execute an Alpha PALcode instruction. (Most of these correspond to
166 dpavlin 22 * OSF1 palcodes, used by for example NetBSD/alpha.)
167 dpavlin 14 */
168     void alpha_palcode(struct cpu *cpu, uint32_t palcode)
169     {
170 dpavlin 32 uint64_t a0 = cpu->cd.alpha.r[ALPHA_A0], a1 = cpu->cd.alpha.r[ALPHA_A1];
171    
172 dpavlin 14 switch (palcode) {
173 dpavlin 32 case 0x02: /* PAL_draina */
174     /* TODO? */
175     break;
176 dpavlin 14 case 0x10: /* PAL_OSF1_rdmces */
177 dpavlin 32 /* TODO. Return Machine Check status in v0. */
178     cpu->cd.alpha.r[ALPHA_V0] = 0;
179 dpavlin 14 break;
180     case 0x11: /* PAL_OSF1_wrmces */
181 dpavlin 32 /* TODO. Clear Machine Check and Error status. */
182 dpavlin 14 break;
183     case 0x2b: /* PAL_OSF1_wrfen */
184     /* Floating point enable: a0 = 1 or 0. */
185     /* TODO */
186     break;
187 dpavlin 24 case 0x2d: /* PAL_OSF1_wrvptptr */
188 dpavlin 32 /* Write Virtual Page Table Pointer. a0 = value */
189     cpu->cd.alpha.vptptr = a0;
190 dpavlin 24 break;
191     case 0x30: /* PAL_OSF1_swpctx */
192 dpavlin 32 /* Save old context: */
193     store_64bit_word(cpu, cpu->cd.alpha.ctx + 0,
194     cpu->cd.alpha.pcb.apcb_ksp);
195     store_64bit_word(cpu, cpu->cd.alpha.ctx + 8,
196     cpu->cd.alpha.pcb.apcb_usp);
197     store_64bit_word(cpu, cpu->cd.alpha.ctx + 16,
198     cpu->cd.alpha.pcb.apcb_ptbr);
199     store_32bit_word(cpu, cpu->cd.alpha.ctx + 24,
200     cpu->cd.alpha.pcb.apcb_cpc);
201     store_32bit_word(cpu, cpu->cd.alpha.ctx + 28,
202     cpu->cd.alpha.pcb.apcb_asn);
203     store_64bit_word(cpu, cpu->cd.alpha.ctx + 32,
204     cpu->cd.alpha.pcb.apcb_unique);
205     store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
206     cpu->cd.alpha.pcb.apcb_flags);
207     store_64bit_word(cpu, cpu->cd.alpha.ctx + 48,
208     cpu->cd.alpha.pcb.apcb_decrsv0);
209     store_64bit_word(cpu, cpu->cd.alpha.ctx + 56,
210     cpu->cd.alpha.pcb.apcb_decrsv1);
211     /* Load new context: */
212     cpu->cd.alpha.ctx = a0;
213     cpu->cd.alpha.pcb.apcb_ksp =
214     load_64bit_word(cpu, cpu->cd.alpha.ctx + 0);
215     cpu->cd.alpha.pcb.apcb_usp =
216     load_64bit_word(cpu, cpu->cd.alpha.ctx + 8);
217     cpu->cd.alpha.pcb.apcb_ptbr =
218     load_64bit_word(cpu, cpu->cd.alpha.ctx + 16);
219     cpu->cd.alpha.pcb.apcb_cpc =
220     load_64bit_word(cpu, cpu->cd.alpha.ctx + 24);
221     cpu->cd.alpha.pcb.apcb_asn =
222     load_64bit_word(cpu, cpu->cd.alpha.ctx + 28);
223     cpu->cd.alpha.pcb.apcb_unique =
224     load_64bit_word(cpu, cpu->cd.alpha.ctx + 32);
225     cpu->cd.alpha.pcb.apcb_flags =
226     load_64bit_word(cpu, cpu->cd.alpha.ctx + 40);
227     cpu->cd.alpha.pcb.apcb_decrsv0 =
228     load_64bit_word(cpu, cpu->cd.alpha.ctx + 48);
229     cpu->cd.alpha.pcb.apcb_decrsv1 =
230     load_64bit_word(cpu, cpu->cd.alpha.ctx + 56);
231 dpavlin 24 break;
232 dpavlin 22 case 0x31: /* PAL_OSF1_wrval */
233     /* a0 = value */
234 dpavlin 32 cpu->cd.alpha.sysvalue = a0;
235 dpavlin 22 break;
236     case 0x32: /* PAL_OSF1_rdval */
237     /* return: v0 = value */
238     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.sysvalue;
239     break;
240 dpavlin 14 case 0x33: /* PAL_OSF1_tbi */
241 dpavlin 32 /*
242     * a0 = op, a1 = vaddr
243     */
244     fatal("[ Alpha PALcode: PAL_OSF1_tbi: a0=%"PRIi64" a1=0x%"
245     PRIx64" ]\n", (int64_t)a0, (uint64_t)a1);
246     cpu->invalidate_translation_caches(cpu, a1, INVALIDATE_VADDR);
247 dpavlin 14 break;
248     case 0x34: /* PAL_OSF1_wrent (Write System Entry Address) */
249     /* a0 = new vector, a1 = vector selector */
250 dpavlin 32 if (a1 < N_ALPHA_KENTRY)
251     cpu->cd.alpha.kentry[a1] = a0;
252     else {
253     fatal("[ Alpha PALcode: PAL_OSF1_wrent: attempt to "
254     "write to non-implemented selector %i ]\n",
255     (int)a1);
256     cpu->running = 0;
257     }
258 dpavlin 14 break;
259     case 0x35: /* PAL_OSF1_swpipl */
260     /* a0 = new ipl, v0 = return old ipl */
261     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ipl;
262 dpavlin 32 cpu->cd.alpha.ipl = a0;
263 dpavlin 14 break;
264     case 0x36: /* PAL_OSF1_rdps */
265     /* TODO */
266     cpu->cd.alpha.r[ALPHA_V0] = 0;
267     break;
268     case 0x37: /* PAL_OSF1_wrkgp */
269     /* "clobbers a0, t0, t8-t11" according to comments in
270     NetBSD sources */
271 dpavlin 32 cpu->cd.alpha.kgp = a0;
272 dpavlin 14 break;
273 dpavlin 32 case 0x38: /* PAL_OSF1_wrusp */
274     /* a0 = value */
275     cpu->cd.alpha.pcb.apcb_usp = a0;
276     break;
277     case 0x3a: /* PAL_OSF1_rdusp */
278     /* return: v0 = value */
279     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.pcb.apcb_usp;
280     break;
281 dpavlin 14 case 0x3c: /* PAL_OSF1_whami */
282     /* Returns CPU id in v0: */
283     cpu->cd.alpha.r[ALPHA_V0] = cpu->cpu_id;
284     break;
285 dpavlin 22 case 0x81: /* PAL_bugchk */
286     cpu->running = 0;
287     break;
288 dpavlin 14 case 0x83: /* PAL_OSF1_syscall */
289     if (cpu->machine->userland_emul != NULL)
290     useremul_syscall(cpu, 0);
291     else {
292     fatal("[ Alpha PALcode: syscall, but no"
293     " syscall handler? ]\n");
294     cpu->running = 0;
295     }
296     break;
297     case 0x86: /* PAL_OSF1_imb */
298     /* TODO */
299     break;
300 dpavlin 32 case 0x3fffffc:
301     fatal("[ Alpha: KENTRY not set! Halting. ]");
302     cpu->running = 0;
303     break;
304 dpavlin 24 case 0x3fffffd:
305     fatal("[ Alpha PALcode: Fixup: TODO ]\n");
306     /* Return from the fixup call. */
307     cpu->cd.alpha.r[ALPHA_V0] = 0; /* Success? */
308     cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
309     break;
310 dpavlin 14 case 0x3fffffe:
311     alpha_prom_call(cpu);
312     break;
313     default:fatal("[ Alpha PALcode 0x%x unimplemented! ]\n", palcode);
314     cpu->running = 0;
315     }
316     }
317    
318    
319     #endif /* ENABLE_ALPHA */
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