/[gxemul]/trunk/src/cpus/cpu_alpha_palcode.c
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Annotation of /trunk/src/cpus/cpu_alpha_palcode.c

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Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 10172 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 dpavlin 14 /*
2 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 32 * $Id: cpu_alpha_palcode.c,v 1.15 2006/10/08 02:28:58 debug Exp $
29 dpavlin 14 *
30     * Alpha PALcode-related functionality.
31 dpavlin 32 *
32     * (See http://www.alphalinux.org/docs/alphaahb.html for good descriptions
33     * of many PALcode functions.)
34 dpavlin 14 */
35    
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40     #include <ctype.h>
41    
42     #include "misc.h"
43    
44    
45     #ifndef ENABLE_ALPHA
46    
47    
48     #include "cpu_alpha.h"
49    
50    
51     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
52     { buf[0]='\0'; }
53     void alpha_palcode(struct cpu *cpu, uint32_t palcode) { }
54    
55    
56     #else /* ENABLE_ALPHA */
57    
58    
59 dpavlin 32 #include "alpha_prom.h"
60 dpavlin 14 #include "console.h"
61     #include "cpu.h"
62     #include "machine.h"
63     #include "memory.h"
64     #include "symbol.h"
65    
66    
67     /*
68     * alpha_palcode_name():
69     *
70     * Return the name of a PALcode number, as a string.
71     */
72     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
73     {
74     switch (palcode) {
75     case 0x10: snprintf(buf, buflen, "PAL_OSF1_rdmces"); break;
76     case 0x11: snprintf(buf, buflen, "PAL_OSF1_wrmces"); break;
77     case 0x2b: snprintf(buf, buflen, "PAL_OSF1_wrfen"); break;
78     case 0x2d: snprintf(buf, buflen, "PAL_OSF1_wrvptptr"); break;
79     case 0x30: snprintf(buf, buflen, "PAL_OSF1_swpctx"); break;
80     case 0x31: snprintf(buf, buflen, "PAL_OSF1_wrval"); break;
81     case 0x32: snprintf(buf, buflen, "PAL_OSF1_rdval"); break;
82     case 0x33: snprintf(buf, buflen, "PAL_OSF1_tbi"); break;
83     case 0x34: snprintf(buf, buflen, "PAL_OSF1_wrent"); break;
84     case 0x35: snprintf(buf, buflen, "PAL_OSF1_swpipl"); break;
85     case 0x36: snprintf(buf, buflen, "PAL_OSF1_rdps"); break;
86     case 0x37: snprintf(buf, buflen, "PAL_OSF1_wrkgp"); break;
87     case 0x38: snprintf(buf, buflen, "PAL_OSF1_wrusp"); break;
88     case 0x39: snprintf(buf, buflen, "PAL_OSF1_wrperfmon"); break;
89     case 0x3a: snprintf(buf, buflen, "PAL_OSF1_rdusp"); break;
90     case 0x3c: snprintf(buf, buflen, "PAL_OSF1_whami"); break;
91     case 0x3d: snprintf(buf, buflen, "PAL_OSF1_retsys"); break;
92     case 0x3f: snprintf(buf, buflen, "PAL_OSF1_rti"); break;
93 dpavlin 22 case 0x81: snprintf(buf, buflen, "PAL_bugchk"); break;
94 dpavlin 14 case 0x83: snprintf(buf, buflen, "PAL_OSF1_callsys"); break;
95     case 0x86: snprintf(buf, buflen, "PAL_OSF1_imb"); break;
96     case 0x92: snprintf(buf, buflen, "PAL_OSF1_urti"); break;
97     case 0x3fffffe: snprintf(buf, buflen, "GXemul_PROM"); break;
98 dpavlin 32 default:snprintf(buf, buflen, "UNKNOWN 0x%"PRIx32, palcode);
99 dpavlin 14 }
100     }
101    
102    
103     /*
104     * alpha_prom_call():
105     */
106     void alpha_prom_call(struct cpu *cpu)
107     {
108 dpavlin 32 uint64_t addr, a1 = cpu->cd.alpha.r[ALPHA_A1];
109     uint64_t a2 = cpu->cd.alpha.r[ALPHA_A2], a3 = cpu->cd.alpha.r[ALPHA_A3];
110     uint64_t len;
111     char *s = "";
112 dpavlin 14
113     switch (cpu->cd.alpha.r[ALPHA_A0]) {
114 dpavlin 32
115     case PROM_R_PUTS:
116     /* a1 = channel, a2 = ptr to buf, a3 = len */
117     for (addr = a2; addr < a2 + a3; addr ++) {
118 dpavlin 14 unsigned char ch;
119     cpu->memory_rw(cpu, cpu->mem, addr, &ch, sizeof(ch),
120     MEM_READ, CACHE_DATA | NO_EXCEPTIONS);
121     console_putchar(cpu->machine->main_console_handle, ch);
122     }
123 dpavlin 32 cpu->cd.alpha.r[ALPHA_V0] = a3;
124 dpavlin 14 break;
125 dpavlin 32
126     case PROM_R_GETENV:
127     /* a1 = variable id, a2 = char *buf, a3 = bufsize */
128     switch (a1) {
129     case PROM_E_BOOTED_DEV:
130     s = ""; /* TODO */
131     break;
132     case PROM_E_BOOTED_FILE:
133     s = cpu->machine->boot_kernel_filename;
134     break;
135     case PROM_E_BOOTED_OSFLAGS:
136     s = cpu->machine->boot_string_argument;
137     break;
138     case PROM_E_TTY_DEV:
139     s = ""; /* TODO */
140     break;
141     default:fatal("[ Alpha PALcode: GXemul PROM getenv %i: TODO "
142     "]\n", cpu->cd.alpha.r[ALPHA_A1]);
143     cpu->running = 0;
144     }
145     /* Copy at most a3 bytes. */
146     len = a3;
147     if (strlen(s) < len)
148     len = strlen(s) + 1;
149     store_buf(cpu, a2, s, len);
150 dpavlin 14 break;
151 dpavlin 32
152 dpavlin 24 default:fatal("[ Alpha PALcode: GXemul PROM call, a0=0x%"PRIx64" ]\n",
153     (uint64_t) cpu->cd.alpha.r[ALPHA_A0]);
154 dpavlin 14 cpu->running = 0;
155     }
156    
157     /* Return from the PROM call. */
158     cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
159     }
160    
161    
162     /*
163     * alpha_palcode():
164     *
165     * Execute an Alpha PALcode instruction. (Most of these correspond to
166 dpavlin 22 * OSF1 palcodes, used by for example NetBSD/alpha.)
167 dpavlin 14 */
168     void alpha_palcode(struct cpu *cpu, uint32_t palcode)
169     {
170 dpavlin 32 uint64_t a0 = cpu->cd.alpha.r[ALPHA_A0], a1 = cpu->cd.alpha.r[ALPHA_A1];
171    
172 dpavlin 14 switch (palcode) {
173 dpavlin 32 case 0x02: /* PAL_draina */
174     /* TODO? */
175     break;
176 dpavlin 14 case 0x10: /* PAL_OSF1_rdmces */
177 dpavlin 32 /* TODO. Return Machine Check status in v0. */
178     cpu->cd.alpha.r[ALPHA_V0] = 0;
179 dpavlin 14 break;
180     case 0x11: /* PAL_OSF1_wrmces */
181 dpavlin 32 /* TODO. Clear Machine Check and Error status. */
182 dpavlin 14 break;
183     case 0x2b: /* PAL_OSF1_wrfen */
184     /* Floating point enable: a0 = 1 or 0. */
185     /* TODO */
186     break;
187 dpavlin 24 case 0x2d: /* PAL_OSF1_wrvptptr */
188 dpavlin 32 /* Write Virtual Page Table Pointer. a0 = value */
189     cpu->cd.alpha.vptptr = a0;
190 dpavlin 24 break;
191     case 0x30: /* PAL_OSF1_swpctx */
192 dpavlin 32 /* Save old context: */
193     store_64bit_word(cpu, cpu->cd.alpha.ctx + 0,
194     cpu->cd.alpha.pcb.apcb_ksp);
195     store_64bit_word(cpu, cpu->cd.alpha.ctx + 8,
196     cpu->cd.alpha.pcb.apcb_usp);
197     store_64bit_word(cpu, cpu->cd.alpha.ctx + 16,
198     cpu->cd.alpha.pcb.apcb_ptbr);
199     store_32bit_word(cpu, cpu->cd.alpha.ctx + 24,
200     cpu->cd.alpha.pcb.apcb_cpc);
201     store_32bit_word(cpu, cpu->cd.alpha.ctx + 28,
202     cpu->cd.alpha.pcb.apcb_asn);
203     store_64bit_word(cpu, cpu->cd.alpha.ctx + 32,
204     cpu->cd.alpha.pcb.apcb_unique);
205     store_64bit_word(cpu, cpu->cd.alpha.ctx + 40,
206     cpu->cd.alpha.pcb.apcb_flags);
207     store_64bit_word(cpu, cpu->cd.alpha.ctx + 48,
208     cpu->cd.alpha.pcb.apcb_decrsv0);
209     store_64bit_word(cpu, cpu->cd.alpha.ctx + 56,
210     cpu->cd.alpha.pcb.apcb_decrsv1);
211     /* Load new context: */
212     cpu->cd.alpha.ctx = a0;
213     cpu->cd.alpha.pcb.apcb_ksp =
214     load_64bit_word(cpu, cpu->cd.alpha.ctx + 0);
215     cpu->cd.alpha.pcb.apcb_usp =
216     load_64bit_word(cpu, cpu->cd.alpha.ctx + 8);
217     cpu->cd.alpha.pcb.apcb_ptbr =
218     load_64bit_word(cpu, cpu->cd.alpha.ctx + 16);
219     cpu->cd.alpha.pcb.apcb_cpc =
220     load_64bit_word(cpu, cpu->cd.alpha.ctx + 24);
221     cpu->cd.alpha.pcb.apcb_asn =
222     load_64bit_word(cpu, cpu->cd.alpha.ctx + 28);
223     cpu->cd.alpha.pcb.apcb_unique =
224     load_64bit_word(cpu, cpu->cd.alpha.ctx + 32);
225     cpu->cd.alpha.pcb.apcb_flags =
226     load_64bit_word(cpu, cpu->cd.alpha.ctx + 40);
227     cpu->cd.alpha.pcb.apcb_decrsv0 =
228     load_64bit_word(cpu, cpu->cd.alpha.ctx + 48);
229     cpu->cd.alpha.pcb.apcb_decrsv1 =
230     load_64bit_word(cpu, cpu->cd.alpha.ctx + 56);
231 dpavlin 24 break;
232 dpavlin 22 case 0x31: /* PAL_OSF1_wrval */
233     /* a0 = value */
234 dpavlin 32 cpu->cd.alpha.sysvalue = a0;
235 dpavlin 22 break;
236     case 0x32: /* PAL_OSF1_rdval */
237     /* return: v0 = value */
238     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.sysvalue;
239     break;
240 dpavlin 14 case 0x33: /* PAL_OSF1_tbi */
241 dpavlin 32 /*
242     * a0 = op, a1 = vaddr
243     */
244     fatal("[ Alpha PALcode: PAL_OSF1_tbi: a0=%"PRIi64" a1=0x%"
245     PRIx64" ]\n", (int64_t)a0, (uint64_t)a1);
246     cpu->invalidate_translation_caches(cpu, a1, INVALIDATE_VADDR);
247 dpavlin 14 break;
248     case 0x34: /* PAL_OSF1_wrent (Write System Entry Address) */
249     /* a0 = new vector, a1 = vector selector */
250 dpavlin 32 if (a1 < N_ALPHA_KENTRY)
251     cpu->cd.alpha.kentry[a1] = a0;
252     else {
253     fatal("[ Alpha PALcode: PAL_OSF1_wrent: attempt to "
254     "write to non-implemented selector %i ]\n",
255     (int)a1);
256     cpu->running = 0;
257     }
258 dpavlin 14 break;
259     case 0x35: /* PAL_OSF1_swpipl */
260     /* a0 = new ipl, v0 = return old ipl */
261     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.ipl;
262 dpavlin 32 cpu->cd.alpha.ipl = a0;
263 dpavlin 14 break;
264     case 0x36: /* PAL_OSF1_rdps */
265     /* TODO */
266     cpu->cd.alpha.r[ALPHA_V0] = 0;
267     break;
268     case 0x37: /* PAL_OSF1_wrkgp */
269     /* "clobbers a0, t0, t8-t11" according to comments in
270     NetBSD sources */
271 dpavlin 32 cpu->cd.alpha.kgp = a0;
272 dpavlin 14 break;
273 dpavlin 32 case 0x38: /* PAL_OSF1_wrusp */
274     /* a0 = value */
275     cpu->cd.alpha.pcb.apcb_usp = a0;
276     break;
277     case 0x3a: /* PAL_OSF1_rdusp */
278     /* return: v0 = value */
279     cpu->cd.alpha.r[ALPHA_V0] = cpu->cd.alpha.pcb.apcb_usp;
280     break;
281 dpavlin 14 case 0x3c: /* PAL_OSF1_whami */
282     /* Returns CPU id in v0: */
283     cpu->cd.alpha.r[ALPHA_V0] = cpu->cpu_id;
284     break;
285 dpavlin 22 case 0x81: /* PAL_bugchk */
286     cpu->running = 0;
287     break;
288 dpavlin 14 case 0x83: /* PAL_OSF1_syscall */
289     if (cpu->machine->userland_emul != NULL)
290     useremul_syscall(cpu, 0);
291     else {
292     fatal("[ Alpha PALcode: syscall, but no"
293     " syscall handler? ]\n");
294     cpu->running = 0;
295     }
296     break;
297     case 0x86: /* PAL_OSF1_imb */
298     /* TODO */
299     break;
300 dpavlin 32 case 0x3fffffc:
301     fatal("[ Alpha: KENTRY not set! Halting. ]");
302     cpu->running = 0;
303     break;
304 dpavlin 24 case 0x3fffffd:
305     fatal("[ Alpha PALcode: Fixup: TODO ]\n");
306     /* Return from the fixup call. */
307     cpu->cd.alpha.r[ALPHA_V0] = 0; /* Success? */
308     cpu->pc = cpu->cd.alpha.r[ALPHA_RA];
309     break;
310 dpavlin 14 case 0x3fffffe:
311     alpha_prom_call(cpu);
312     break;
313     default:fatal("[ Alpha PALcode 0x%x unimplemented! ]\n", palcode);
314     cpu->running = 0;
315     }
316     }
317    
318    
319     #endif /* ENABLE_ALPHA */

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