/[gxemul]/trunk/src/cpus/cpu_alpha_instr_loadstore.c
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Contents of /trunk/src/cpus/cpu_alpha_instr_loadstore.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
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File size: 8790 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_alpha_instr_loadstore.c,v 1.3 2006/01/01 16:08:25 debug Exp $
29 *
30 * Alpha load/store instructions. (Included from cpu_alpha_instr_inc.c.)
31 *
32 *
33 * Load/store instructions have the following arguments:
34 *
35 * arg[0] = pointer to the register to load to or store from (uint64_t)
36 * arg[1] = pointer to the base register (uint64_t)
37 * arg[2] = offset (as an int32_t)
38 *
39 * NOTE:
40 * Alpha byte and word loads (8- and 16-bit) are unsigned, while
41 * 32-bit long words are sign-extended up to 64 bits during a load!
42 */
43
44
45 #ifndef LS_IGNORE_OFFSET
46 #ifndef LS_ALIGN_CHECK
47 static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
48 {
49 #ifdef LS_B
50 unsigned char data[1];
51 #endif
52 #ifdef LS_W
53 unsigned char data[2];
54 #endif
55 #ifdef LS_L
56 unsigned char data[4];
57 #endif
58 #ifdef LS_Q
59 unsigned char data[8];
60 #endif
61 uint64_t addr = *((uint64_t *)ic->arg[1]);
62 uint64_t data_x;
63
64 addr += (int32_t)ic->arg[2];
65 #ifdef LS_UNALIGNED
66 addr &= ~7;
67 #endif
68
69 #ifdef LS_LOAD
70 /* Load: */
71 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
72 MEM_READ, CACHE_DATA)) {
73 fatal("store failed: TODO\n");
74 exit(1);
75 }
76
77 data_x = data[0];
78 #ifndef LS_B
79 data_x += (data[1] << 8);
80 #ifndef LS_W
81 data_x += (data[2] << 16);
82 data_x += ((uint64_t)data[3] << 24);
83 #ifdef LS_L
84 data_x = (int64_t)(int32_t)data_x;
85 #endif
86 #ifndef LS_L
87 data_x += ((uint64_t)data[4] << 32);
88 data_x += ((uint64_t)data[5] << 40);
89 data_x += ((uint64_t)data[6] << 48);
90 data_x += ((uint64_t)data[7] << 56);
91 #endif
92 #endif
93 #endif
94 *((uint64_t *)ic->arg[0]) = data_x;
95 #else
96 /* Store: */
97 data_x = *((uint64_t *)ic->arg[0]);
98 data[0] = data_x;
99 #ifndef LS_B
100 data[1] = data_x >> 8;
101 #ifndef LS_W
102 data[2] = data_x >> 16;
103 data[3] = data_x >> 24;
104 #ifndef LS_L
105 data[4] = data_x >> 32;
106 data[5] = data_x >> 40;
107 data[6] = data_x >> 48;
108 data[7] = data_x >> 56;
109 #endif
110 #endif
111 #endif
112
113 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
114 MEM_WRITE, CACHE_DATA)) {
115 fatal("store failed: TODO\n");
116 exit(1);
117 }
118
119 #ifdef LS_LLSC
120 #ifndef LS_LOAD
121 *((uint64_t *)ic->arg[0]) = 1;
122 #endif
123 #endif
124
125 #endif
126 }
127 #endif
128 #endif
129
130
131 static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
132 {
133 int first, a, b, c;
134 uint64_t addr;
135
136 addr = (*((uint64_t *)ic->arg[1]))
137 #ifndef LS_IGNORE_OFFSET
138 + (int32_t)ic->arg[2]
139 #endif
140 ;
141
142 #ifdef LS_UNALIGNED
143 addr &= ~7;
144 #endif
145
146 #ifdef LS_LLSC
147 #ifdef LS_LOAD
148 /* TODO: cache-line size! */
149 cpu->cd.alpha.load_linked_addr = addr & ~63;
150 cpu->cd.alpha.ll_flag = 1;
151 #else
152 /* TODO: only invalidate per cache line, not everything! */
153 if (cpu->cd.alpha.ll_flag == 1) {
154 int i;
155 for (i=0; i<cpu->machine->ncpus; i++)
156 cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
157 } else {
158 *((uint64_t *)ic->arg[0]) = 0;
159 return;
160 }
161 #endif
162 #endif
163
164 first = addr >> ALPHA_TOPSHIFT;
165 a = (addr >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1);
166 b = (addr >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1);
167 c = addr & 8191;
168
169 #ifdef LS_ALIGN_CHECK
170 #ifndef LS_B
171 if (c &
172 #ifdef LS_W
173 1
174 #endif
175 #ifdef LS_L
176 3
177 #endif
178 #ifdef LS_Q
179 7
180 #endif
181 ) {
182 LS_GENERIC_N(cpu, ic);
183 return;
184 }
185 else
186 #endif
187 #endif
188
189 if (first == 0) {
190 struct alpha_vph_page *vph_p;
191 unsigned char *page;
192 vph_p = cpu->cd.alpha.vph_table0[a];
193 #ifdef LS_LOAD
194 page = vph_p->host_load[b];
195 #else
196 page = vph_p->host_store[b];
197 #endif
198 if (page != NULL) {
199 #ifdef LS_LOAD
200 #ifdef HOST_BIG_ENDIAN
201 uint64_t data_x;
202 data_x = page[c];
203 #ifndef LS_B
204 data_x += (page[c+1] << 8);
205 #ifndef LS_W
206 data_x += (page[c+2] << 16);
207 data_x += ((uint64_t)page[c+3] << 24);
208 #ifndef LS_L
209 data_x += ((uint64_t)page[c+4] << 32);
210 data_x += ((uint64_t)page[c+5] << 40);
211 data_x += ((uint64_t)page[c+6] << 48);
212 data_x += ((uint64_t)page[c+7] << 56);
213 #endif
214 #endif
215 #endif
216 #ifdef LS_L
217 *((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
218 #else
219 *((uint64_t *)ic->arg[0]) = data_x;
220 #endif
221 #else
222 #ifdef LS_B
223 *((uint64_t *)ic->arg[0]) = page[c];
224 #endif
225 #ifdef LS_W
226 uint16_t d = *((uint16_t *) (page + c));
227 *((uint64_t *)ic->arg[0]) = d;
228 #endif
229 #ifdef LS_L
230 int32_t d = *((int32_t *) (page + c));
231 *((uint64_t *)ic->arg[0]) = (int64_t)d;
232 #endif
233 #ifdef LS_Q
234 uint64_t d = *((uint64_t *) (page + c));
235 *((uint64_t *)ic->arg[0]) = d;
236 #endif
237 #endif
238 #else
239 /* Store: */
240 #ifdef HOST_BIG_ENDIAN
241 uint64_t data_x = *((uint64_t *)ic->arg[0]);
242 page[c] = data_x;
243 #ifndef LS_B
244 page[c+1] = data_x >> 8;
245 #ifndef LS_W
246 page[c+2] = data_x >> 16;
247 page[c+3] = data_x >> 24;
248 #ifndef LS_L
249 page[c+4] = data_x >> 32;
250 page[c+5] = data_x >> 40;
251 page[c+6] = data_x >> 48;
252 page[c+7] = data_x >> 56;
253 #endif
254 #endif
255 #endif
256 #else
257 /* Native byte order: */
258 #ifdef LS_B
259 page[c] = *((uint64_t *)ic->arg[0]);
260 #endif
261 #ifdef LS_W
262 uint32_t d = *((uint64_t *)ic->arg[0]);
263 *((uint16_t *) (page + c)) = d;
264 #endif
265 #ifdef LS_L
266 uint32_t d = *((uint64_t *)ic->arg[0]);
267 *((uint32_t *) (page + c)) = d;
268 #endif
269 #ifdef LS_Q
270 uint64_t d = *((uint64_t *)ic->arg[0]);
271 *((uint64_t *) (page + c)) = d;
272 #endif
273 #endif
274
275 #ifdef LS_LLSC
276 #ifndef LS_LOAD
277 *((uint64_t *)ic->arg[0]) = 1;
278 #endif
279 #endif
280
281 #endif /* !LS_LOAD */
282 } else
283 LS_GENERIC_N(cpu, ic);
284 } else if (first == ALPHA_TOP_KERNEL) {
285 struct alpha_vph_page *vph_p;
286 unsigned char *page;
287 vph_p = cpu->cd.alpha.vph_table0_kernel[a];
288 #ifdef LS_LOAD
289 page = vph_p->host_load[b];
290 #else
291 page = vph_p->host_store[b];
292 #endif
293 if (page != NULL) {
294 #ifdef LS_LOAD
295 #ifdef HOST_BIG_ENDIAN
296 uint64_t data_x;
297 data_x = page[c];
298 #ifndef LS_B
299 data_x += (page[c+1] << 8);
300 #ifndef LS_W
301 data_x += (page[c+2] << 16);
302 data_x += ((uint64_t)page[c+3] << 24);
303 #ifndef LS_L
304 data_x += ((uint64_t)page[c+4] << 32);
305 data_x += ((uint64_t)page[c+5] << 40);
306 data_x += ((uint64_t)page[c+6] << 48);
307 data_x += ((uint64_t)page[c+7] << 56);
308 #endif
309 #endif
310 #endif
311 #ifdef LS_L
312 *((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
313 #else
314 *((uint64_t *)ic->arg[0]) = data_x;
315 #endif
316 #else
317 #ifdef LS_B
318 *((uint64_t *)ic->arg[0]) = page[c];
319 #endif
320 #ifdef LS_W
321 uint16_t d = *((uint16_t *) (page + c));
322 *((uint64_t *)ic->arg[0]) = d;
323 #endif
324 #ifdef LS_L
325 int32_t d = *((int32_t *) (page + c));
326 *((uint64_t *)ic->arg[0]) = (int64_t)d;
327 #endif
328 #ifdef LS_Q
329 uint64_t d = *((uint64_t *) (page + c));
330 *((uint64_t *)ic->arg[0]) = d;
331 #endif
332 #endif
333 #else
334 /* Store: */
335 #ifdef HOST_BIG_ENDIAN
336 uint64_t data_x = *((uint64_t *)ic->arg[0]);
337 page[c] = data_x;
338 #ifndef LS_B
339 page[c+1] = data_x >> 8;
340 #ifndef LS_W
341 page[c+2] = data_x >> 16;
342 page[c+3] = data_x >> 24;
343 #ifndef LS_L
344 page[c+4] = data_x >> 32;
345 page[c+5] = data_x >> 40;
346 page[c+6] = data_x >> 48;
347 page[c+7] = data_x >> 56;
348 #endif
349 #endif
350 #endif
351 #else
352 /* Native byte order: */
353 #ifdef LS_B
354 page[c] = *((uint64_t *)ic->arg[0]);
355 #endif
356 #ifdef LS_W
357 uint32_t d = *((uint64_t *)ic->arg[0]);
358 *((uint16_t *) (page + c)) = d;
359 #endif
360 #ifdef LS_L
361 uint32_t d = *((uint64_t *)ic->arg[0]);
362 *((uint32_t *) (page + c)) = d;
363 #endif
364 #ifdef LS_Q
365 uint64_t d = *((uint64_t *)ic->arg[0]);
366 *((uint64_t *) (page + c)) = d;
367 #endif
368 #endif
369
370 #ifdef LS_LLSC
371 #ifndef LS_LOAD
372 *((uint64_t *)ic->arg[0]) = 1;
373 #endif
374 #endif
375
376 #endif /* !LS_LOAD */
377 } else
378 LS_GENERIC_N(cpu, ic);
379 } else
380 LS_GENERIC_N(cpu, ic);
381 }
382

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