/[gxemul]/trunk/src/cpus/cpu_alpha_instr_loadstore.c
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Annotation of /trunk/src/cpus/cpu_alpha_instr_loadstore.c

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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 6969 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: cpu_alpha_instr_loadstore.c,v 1.6 2006/12/30 13:30:53 debug Exp $
29 dpavlin 14 *
30     * Alpha load/store instructions. (Included from cpu_alpha_instr_inc.c.)
31     *
32     *
33     * Load/store instructions have the following arguments:
34     *
35     * arg[0] = pointer to the register to load to or store from (uint64_t)
36     * arg[1] = pointer to the base register (uint64_t)
37     * arg[2] = offset (as an int32_t)
38     *
39     * NOTE:
40     * Alpha byte and word loads (8- and 16-bit) are unsigned, while
41     * 32-bit long words are sign-extended up to 64 bits during a load!
42     */
43    
44    
45     #ifndef LS_IGNORE_OFFSET
46     static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
47     {
48     #ifdef LS_B
49     unsigned char data[1];
50     #endif
51     #ifdef LS_W
52     unsigned char data[2];
53     #endif
54     #ifdef LS_L
55     unsigned char data[4];
56     #endif
57     #ifdef LS_Q
58     unsigned char data[8];
59     #endif
60     uint64_t addr = *((uint64_t *)ic->arg[1]);
61     uint64_t data_x;
62    
63     addr += (int32_t)ic->arg[2];
64     #ifdef LS_UNALIGNED
65     addr &= ~7;
66     #endif
67    
68     #ifdef LS_LOAD
69     /* Load: */
70     if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
71     MEM_READ, CACHE_DATA)) {
72     fatal("store failed: TODO\n");
73     exit(1);
74     }
75    
76     data_x = data[0];
77     #ifndef LS_B
78     data_x += (data[1] << 8);
79     #ifndef LS_W
80     data_x += (data[2] << 16);
81 dpavlin 20 data_x += ((uint64_t)data[3] << 24);
82 dpavlin 14 #ifdef LS_L
83     data_x = (int64_t)(int32_t)data_x;
84     #endif
85     #ifndef LS_L
86     data_x += ((uint64_t)data[4] << 32);
87     data_x += ((uint64_t)data[5] << 40);
88     data_x += ((uint64_t)data[6] << 48);
89     data_x += ((uint64_t)data[7] << 56);
90     #endif
91     #endif
92     #endif
93     *((uint64_t *)ic->arg[0]) = data_x;
94     #else
95     /* Store: */
96     data_x = *((uint64_t *)ic->arg[0]);
97     data[0] = data_x;
98     #ifndef LS_B
99     data[1] = data_x >> 8;
100     #ifndef LS_W
101     data[2] = data_x >> 16;
102     data[3] = data_x >> 24;
103     #ifndef LS_L
104     data[4] = data_x >> 32;
105     data[5] = data_x >> 40;
106     data[6] = data_x >> 48;
107     data[7] = data_x >> 56;
108     #endif
109     #endif
110     #endif
111    
112     if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
113     MEM_WRITE, CACHE_DATA)) {
114     fatal("store failed: TODO\n");
115     exit(1);
116     }
117    
118     #ifdef LS_LLSC
119     #ifndef LS_LOAD
120     *((uint64_t *)ic->arg[0]) = 1;
121     #endif
122     #endif
123    
124     #endif
125     }
126     #endif
127    
128    
129     static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
130     {
131 dpavlin 24 unsigned char *page;
132     uint64_t addr = (*((uint64_t *)ic->arg[1]))
133 dpavlin 14 #ifndef LS_IGNORE_OFFSET
134     + (int32_t)ic->arg[2]
135     #endif
136     ;
137    
138 dpavlin 24 const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
139     const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
140     const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
141     uint32_t x1, x2, x3, c;
142     struct DYNTRANS_L2_64_TABLE *l2;
143     struct DYNTRANS_L3_64_TABLE *l3;
144     x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
145     x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
146     x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
147     /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
148     (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
149     l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
150     /* fatal(" l2 = %p\n", l2); */
151     l3 = l2->l3[x2];
152     /* fatal(" l3 = %p\n", l3); */
153     #ifdef LS_LOAD
154     page = l3->host_load[x3];
155     #else
156     page = l3->host_store[x3];
157     #endif
158    
159 dpavlin 14 #ifdef LS_UNALIGNED
160     addr &= ~7;
161     #endif
162    
163     #ifdef LS_LLSC
164     #ifdef LS_LOAD
165     /* TODO: cache-line size! */
166     cpu->cd.alpha.load_linked_addr = addr & ~63;
167     cpu->cd.alpha.ll_flag = 1;
168     #else
169     /* TODO: only invalidate per cache line, not everything! */
170     if (cpu->cd.alpha.ll_flag == 1) {
171     int i;
172     for (i=0; i<cpu->machine->ncpus; i++)
173     cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
174     } else {
175     *((uint64_t *)ic->arg[0]) = 0;
176     return;
177     }
178     #endif
179     #endif
180    
181     c = addr & 8191;
182    
183     #ifndef LS_B
184     if (c &
185     #ifdef LS_W
186     1
187     #endif
188     #ifdef LS_L
189     3
190     #endif
191     #ifdef LS_Q
192     7
193     #endif
194     ) {
195     LS_GENERIC_N(cpu, ic);
196     return;
197     }
198     else
199     #endif
200    
201 dpavlin 24 if (page != NULL) {
202 dpavlin 14 #ifdef LS_LOAD
203     #ifdef HOST_BIG_ENDIAN
204 dpavlin 24 uint64_t data_x;
205     data_x = page[c];
206 dpavlin 14 #ifndef LS_B
207 dpavlin 24 data_x += (page[c+1] << 8);
208 dpavlin 14 #ifndef LS_W
209 dpavlin 24 data_x += (page[c+2] << 16);
210     data_x += ((uint64_t)page[c+3] << 24);
211 dpavlin 14 #ifndef LS_L
212 dpavlin 24 data_x += ((uint64_t)page[c+4] << 32);
213     data_x += ((uint64_t)page[c+5] << 40);
214     data_x += ((uint64_t)page[c+6] << 48);
215     data_x += ((uint64_t)page[c+7] << 56);
216 dpavlin 14 #endif
217     #endif
218     #endif
219     #ifdef LS_L
220 dpavlin 24 *((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
221 dpavlin 14 #else
222 dpavlin 24 *((uint64_t *)ic->arg[0]) = data_x;
223 dpavlin 14 #endif
224     #else
225     #ifdef LS_B
226 dpavlin 24 *((uint64_t *)ic->arg[0]) = page[c];
227 dpavlin 14 #endif
228     #ifdef LS_W
229 dpavlin 24 uint16_t d = *((uint16_t *) (page + c));
230     *((uint64_t *)ic->arg[0]) = d;
231 dpavlin 14 #endif
232     #ifdef LS_L
233 dpavlin 24 int32_t d = *((int32_t *) (page + c));
234     *((uint64_t *)ic->arg[0]) = (int64_t)d;
235 dpavlin 14 #endif
236     #ifdef LS_Q
237 dpavlin 24 uint64_t d = *((uint64_t *) (page + c));
238     *((uint64_t *)ic->arg[0]) = d;
239 dpavlin 14 #endif
240     #endif
241     #else
242 dpavlin 24 /* Store: */
243 dpavlin 14 #ifdef HOST_BIG_ENDIAN
244 dpavlin 24 uint64_t data_x = *((uint64_t *)ic->arg[0]);
245     page[c] = data_x;
246 dpavlin 14 #ifndef LS_B
247 dpavlin 24 page[c+1] = data_x >> 8;
248 dpavlin 14 #ifndef LS_W
249 dpavlin 24 page[c+2] = data_x >> 16;
250     page[c+3] = data_x >> 24;
251 dpavlin 14 #ifndef LS_L
252 dpavlin 24 page[c+4] = data_x >> 32;
253     page[c+5] = data_x >> 40;
254     page[c+6] = data_x >> 48;
255     page[c+7] = data_x >> 56;
256 dpavlin 14 #endif
257     #endif
258     #endif
259     #else
260 dpavlin 24 /* Native byte order: */
261 dpavlin 14 #ifdef LS_B
262 dpavlin 24 page[c] = *((uint64_t *)ic->arg[0]);
263 dpavlin 14 #endif
264     #ifdef LS_W
265 dpavlin 24 uint32_t d = *((uint64_t *)ic->arg[0]);
266     *((uint16_t *) (page + c)) = d;
267 dpavlin 14 #endif
268     #ifdef LS_L
269 dpavlin 24 uint32_t d = *((uint64_t *)ic->arg[0]);
270     *((uint32_t *) (page + c)) = d;
271 dpavlin 14 #endif
272     #ifdef LS_Q
273 dpavlin 24 uint64_t d = *((uint64_t *)ic->arg[0]);
274     *((uint64_t *) (page + c)) = d;
275 dpavlin 14 #endif
276     #endif
277    
278     #ifdef LS_LLSC
279     #ifndef LS_LOAD
280 dpavlin 24 *((uint64_t *)ic->arg[0]) = 1;
281 dpavlin 14 #endif
282     #endif
283    
284     #endif /* !LS_LOAD */
285     } else
286     LS_GENERIC_N(cpu, ic);
287     }
288    

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