/[gxemul]/trunk/src/cpus/cpu_alpha_instr_loadstore.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_alpha_instr_loadstore.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 7028 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_alpha_instr_loadstore.c,v 1.4 2006/04/22 18:28:43 debug Exp $
29 *
30 * Alpha load/store instructions. (Included from cpu_alpha_instr_inc.c.)
31 *
32 *
33 * Load/store instructions have the following arguments:
34 *
35 * arg[0] = pointer to the register to load to or store from (uint64_t)
36 * arg[1] = pointer to the base register (uint64_t)
37 * arg[2] = offset (as an int32_t)
38 *
39 * NOTE:
40 * Alpha byte and word loads (8- and 16-bit) are unsigned, while
41 * 32-bit long words are sign-extended up to 64 bits during a load!
42 */
43
44
45 #ifndef LS_IGNORE_OFFSET
46 #ifndef LS_ALIGN_CHECK
47 static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic)
48 {
49 #ifdef LS_B
50 unsigned char data[1];
51 #endif
52 #ifdef LS_W
53 unsigned char data[2];
54 #endif
55 #ifdef LS_L
56 unsigned char data[4];
57 #endif
58 #ifdef LS_Q
59 unsigned char data[8];
60 #endif
61 uint64_t addr = *((uint64_t *)ic->arg[1]);
62 uint64_t data_x;
63
64 addr += (int32_t)ic->arg[2];
65 #ifdef LS_UNALIGNED
66 addr &= ~7;
67 #endif
68
69 #ifdef LS_LOAD
70 /* Load: */
71 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
72 MEM_READ, CACHE_DATA)) {
73 fatal("store failed: TODO\n");
74 exit(1);
75 }
76
77 data_x = data[0];
78 #ifndef LS_B
79 data_x += (data[1] << 8);
80 #ifndef LS_W
81 data_x += (data[2] << 16);
82 data_x += ((uint64_t)data[3] << 24);
83 #ifdef LS_L
84 data_x = (int64_t)(int32_t)data_x;
85 #endif
86 #ifndef LS_L
87 data_x += ((uint64_t)data[4] << 32);
88 data_x += ((uint64_t)data[5] << 40);
89 data_x += ((uint64_t)data[6] << 48);
90 data_x += ((uint64_t)data[7] << 56);
91 #endif
92 #endif
93 #endif
94 *((uint64_t *)ic->arg[0]) = data_x;
95 #else
96 /* Store: */
97 data_x = *((uint64_t *)ic->arg[0]);
98 data[0] = data_x;
99 #ifndef LS_B
100 data[1] = data_x >> 8;
101 #ifndef LS_W
102 data[2] = data_x >> 16;
103 data[3] = data_x >> 24;
104 #ifndef LS_L
105 data[4] = data_x >> 32;
106 data[5] = data_x >> 40;
107 data[6] = data_x >> 48;
108 data[7] = data_x >> 56;
109 #endif
110 #endif
111 #endif
112
113 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
114 MEM_WRITE, CACHE_DATA)) {
115 fatal("store failed: TODO\n");
116 exit(1);
117 }
118
119 #ifdef LS_LLSC
120 #ifndef LS_LOAD
121 *((uint64_t *)ic->arg[0]) = 1;
122 #endif
123 #endif
124
125 #endif
126 }
127 #endif
128 #endif
129
130
131 static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic)
132 {
133 unsigned char *page;
134 uint64_t addr = (*((uint64_t *)ic->arg[1]))
135 #ifndef LS_IGNORE_OFFSET
136 + (int32_t)ic->arg[2]
137 #endif
138 ;
139
140 const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
141 const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
142 const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
143 uint32_t x1, x2, x3, c;
144 struct DYNTRANS_L2_64_TABLE *l2;
145 struct DYNTRANS_L3_64_TABLE *l3;
146 x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
147 x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
148 x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
149 /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
150 (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
151 l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
152 /* fatal(" l2 = %p\n", l2); */
153 l3 = l2->l3[x2];
154 /* fatal(" l3 = %p\n", l3); */
155 #ifdef LS_LOAD
156 page = l3->host_load[x3];
157 #else
158 page = l3->host_store[x3];
159 #endif
160
161 #ifdef LS_UNALIGNED
162 addr &= ~7;
163 #endif
164
165 #ifdef LS_LLSC
166 #ifdef LS_LOAD
167 /* TODO: cache-line size! */
168 cpu->cd.alpha.load_linked_addr = addr & ~63;
169 cpu->cd.alpha.ll_flag = 1;
170 #else
171 /* TODO: only invalidate per cache line, not everything! */
172 if (cpu->cd.alpha.ll_flag == 1) {
173 int i;
174 for (i=0; i<cpu->machine->ncpus; i++)
175 cpu->machine->cpus[i]->cd.alpha.ll_flag = 0;
176 } else {
177 *((uint64_t *)ic->arg[0]) = 0;
178 return;
179 }
180 #endif
181 #endif
182
183 c = addr & 8191;
184
185 #ifdef LS_ALIGN_CHECK
186 #ifndef LS_B
187 if (c &
188 #ifdef LS_W
189 1
190 #endif
191 #ifdef LS_L
192 3
193 #endif
194 #ifdef LS_Q
195 7
196 #endif
197 ) {
198 LS_GENERIC_N(cpu, ic);
199 return;
200 }
201 else
202 #endif
203 #endif
204
205 if (page != NULL) {
206 #ifdef LS_LOAD
207 #ifdef HOST_BIG_ENDIAN
208 uint64_t data_x;
209 data_x = page[c];
210 #ifndef LS_B
211 data_x += (page[c+1] << 8);
212 #ifndef LS_W
213 data_x += (page[c+2] << 16);
214 data_x += ((uint64_t)page[c+3] << 24);
215 #ifndef LS_L
216 data_x += ((uint64_t)page[c+4] << 32);
217 data_x += ((uint64_t)page[c+5] << 40);
218 data_x += ((uint64_t)page[c+6] << 48);
219 data_x += ((uint64_t)page[c+7] << 56);
220 #endif
221 #endif
222 #endif
223 #ifdef LS_L
224 *((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x;
225 #else
226 *((uint64_t *)ic->arg[0]) = data_x;
227 #endif
228 #else
229 #ifdef LS_B
230 *((uint64_t *)ic->arg[0]) = page[c];
231 #endif
232 #ifdef LS_W
233 uint16_t d = *((uint16_t *) (page + c));
234 *((uint64_t *)ic->arg[0]) = d;
235 #endif
236 #ifdef LS_L
237 int32_t d = *((int32_t *) (page + c));
238 *((uint64_t *)ic->arg[0]) = (int64_t)d;
239 #endif
240 #ifdef LS_Q
241 uint64_t d = *((uint64_t *) (page + c));
242 *((uint64_t *)ic->arg[0]) = d;
243 #endif
244 #endif
245 #else
246 /* Store: */
247 #ifdef HOST_BIG_ENDIAN
248 uint64_t data_x = *((uint64_t *)ic->arg[0]);
249 page[c] = data_x;
250 #ifndef LS_B
251 page[c+1] = data_x >> 8;
252 #ifndef LS_W
253 page[c+2] = data_x >> 16;
254 page[c+3] = data_x >> 24;
255 #ifndef LS_L
256 page[c+4] = data_x >> 32;
257 page[c+5] = data_x >> 40;
258 page[c+6] = data_x >> 48;
259 page[c+7] = data_x >> 56;
260 #endif
261 #endif
262 #endif
263 #else
264 /* Native byte order: */
265 #ifdef LS_B
266 page[c] = *((uint64_t *)ic->arg[0]);
267 #endif
268 #ifdef LS_W
269 uint32_t d = *((uint64_t *)ic->arg[0]);
270 *((uint16_t *) (page + c)) = d;
271 #endif
272 #ifdef LS_L
273 uint32_t d = *((uint64_t *)ic->arg[0]);
274 *((uint32_t *) (page + c)) = d;
275 #endif
276 #ifdef LS_Q
277 uint64_t d = *((uint64_t *)ic->arg[0]);
278 *((uint64_t *) (page + c)) = d;
279 #endif
280 #endif
281
282 #ifdef LS_LLSC
283 #ifndef LS_LOAD
284 *((uint64_t *)ic->arg[0]) = 1;
285 #endif
286 #endif
287
288 #endif /* !LS_LOAD */
289 } else
290 LS_GENERIC_N(cpu, ic);
291 }
292

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