/[gxemul]/trunk/src/cpus/cpu_alpha_instr_alu.c
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Contents of /trunk/src/cpus/cpu_alpha_instr_alu.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 2 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_alpha_instr_alu.c,v 1.2 2006/01/01 16:08:25 debug Exp $
29 *
30 * Alpha ALU instructions. (Included from tmp_alpha_misc.c.)
31 *
32 *
33 * Most ALU instructions have the following arguments:
34 *
35 * arg[0] = pointer to destination uint64_t
36 * arg[1] = pointer to source uint64_t nr 1
37 * arg[2] = pointer to source uint64_t nr 2
38 *
39 * or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
40 *
41 * The main function groups are:
42 *
43 * ALU_INS inserts
44 * ALU_EXT extracts
45 * ALU_MSK masks
46 * ALU_CMOV conditional moves
47 * ALU_CMP compares
48 * none of the above everything else (add, sub, ...)
49 */
50
51 void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
52 {
53 #ifdef ALU_INS
54
55 uint64_t x = *((uint64_t *)ic->arg[1]);
56 int r = (
57 #ifdef ALU_IMM
58 ic->arg[2]
59 #else
60 (*((uint64_t *)ic->arg[2]))
61 #endif
62 & 7) * 8;
63
64 #ifdef ALU_B
65 x &= 0xff;
66 #endif
67 #ifdef ALU_W
68 x &= 0xffff;
69 #endif
70 #ifdef ALU_L
71 x &= 0xffffffffULL;
72 #endif
73
74 #ifdef ALU_LO
75 x <<= r;
76 #else
77 r = 64 - r;
78 if (r == 64)
79 x = 0;
80 else
81 x >>= r;
82 #endif
83 *((uint64_t *)ic->arg[0]) = x;
84
85 #else /* ! INS */
86
87 #ifdef ALU_EXT
88
89 uint64_t x = *((uint64_t *)ic->arg[1]);
90 int r = (
91 #ifdef ALU_IMM
92 ic->arg[2]
93 #else
94 (*((uint64_t *)ic->arg[2]))
95 #endif
96 & 7) * 8;
97 #ifdef ALU_LO
98 x >>= r;
99 #else
100 r = 64 - r;
101 if (r != 64)
102 x <<= r;
103 #endif
104 #ifdef ALU_B
105 x &= 0xff;
106 #endif
107 #ifdef ALU_W
108 x &= 0xffff;
109 #endif
110 #ifdef ALU_L
111 x &= 0xffffffffULL;
112 #endif
113 *((uint64_t *)ic->arg[0]) = x;
114
115 #else /* ! EXT */
116
117 #ifdef ALU_MSK
118
119 uint64_t x = *((uint64_t *)ic->arg[1]);
120 #ifdef ALU_B
121 uint64_t mask = 0x00000000000000ffULL;
122 #endif
123 #ifdef ALU_W
124 uint64_t mask = 0x000000000000ffffULL;
125 #endif
126 #ifdef ALU_L
127 uint64_t mask = 0x00000000ffffffffULL;
128 #endif
129 #ifdef ALU_Q
130 uint64_t mask = 0xffffffffffffffffULL;
131 #endif
132 int r = (
133 #ifdef ALU_IMM
134 ic->arg[2]
135 #else
136 (*((uint64_t *)ic->arg[2]))
137 #endif
138 & 7) * 8;
139
140 #ifdef ALU_LO
141 mask <<= r;
142 #else
143 if (r == 0)
144 mask = 0;
145 else
146 mask >>= (64 - r);
147 #endif
148
149 *((uint64_t *)ic->arg[0]) = x & ~mask;
150
151 #else /* !MSK */
152
153 #ifdef ALU_CMOV
154
155 if (
156 #ifdef ALU_CMOV_lbc
157 !(
158 #endif
159 (*((int64_t *)ic->arg[1]))
160 #ifdef ALU_CMOV_eq
161 == 0
162 #endif
163 #ifdef ALU_CMOV_ne
164 != 0
165 #endif
166 #ifdef ALU_CMOV_le
167 <= 0
168 #endif
169 #ifdef ALU_CMOV_lt
170 < 0
171 #endif
172 #ifdef ALU_CMOV_ge
173 >= 0
174 #endif
175 #ifdef ALU_CMOV_gt
176 > 0
177 #endif
178 #ifdef ALU_CMOV_lbs
179 & 1
180 #endif
181 #ifdef ALU_CMOV_lbc
182 & 1)
183 #endif
184 )
185 *((uint64_t *)ic->arg[0]) =
186 #ifdef ALU_IMM
187 (uint64_t)ic->arg[2]
188 #else
189 (*((uint64_t *)ic->arg[2]))
190 #endif
191 ;
192
193 #else /* ! CMOV */
194
195 #ifdef ALU_CMP
196
197 uint64_t x;
198
199 x = (*((
200 #ifdef ALU_UNSIGNED
201 uint64_t
202 #else
203 int64_t
204 #endif
205 *)ic->arg[1]))
206
207 #ifdef ALU_CMP_EQ
208 ==
209 #endif
210 #ifdef ALU_CMP_LE
211 <=
212 #endif
213 #ifdef ALU_CMP_LT
214 <
215 #endif
216
217 #ifdef ALU_IMM
218 #ifdef ALU_UNSIGNED
219 (uint64_t)ic->arg[2]
220 #else
221 (int64_t)ic->arg[2]
222 #endif
223 #else
224 #ifdef ALU_UNSIGNED
225 (*((uint64_t *)ic->arg[2]))
226 #else
227 (*((int64_t *)ic->arg[2]))
228 #endif
229 #endif
230 ;
231
232 #else /* !ALU_CMP */
233
234 #ifdef ALU_LONG
235 /* Long */
236 int32_t x;
237 #else
238 /* Quad */
239 int64_t x;
240 #endif
241
242 #ifdef ALU_ZAP
243 /* Prepare for zapping: */
244 uint64_t zapmask = 0xffffffffffffffffULL;
245 int zapbytes =
246 #ifdef ALU_NOT
247 ~
248 #endif
249 #ifdef ALU_IMM
250 (int64_t)ic->arg[2]
251 #else
252 (*((uint64_t *)ic->arg[2]))
253 #endif
254 ;
255 if (zapbytes & 0x80)
256 zapmask &= ~0xff00000000000000ULL;
257 if (zapbytes & 0x40)
258 zapmask &= ~0xff000000000000ULL;
259 if (zapbytes & 0x20)
260 zapmask &= ~0xff0000000000ULL;
261 if (zapbytes & 0x10)
262 zapmask &= ~0xff00000000ULL;
263 if (zapbytes & 0x08)
264 zapmask &= ~0xff000000ULL;
265 if (zapbytes & 0x04)
266 zapmask &= ~0xff0000ULL;
267 if (zapbytes & 0x02)
268 zapmask &= ~0xff00ULL;
269 if (zapbytes & 0x01)
270 zapmask &= ~0xffULL;
271 #endif /* ZAP */
272
273 x = (
274 #ifdef ALU_SRA
275 (int64_t)
276 #endif
277 (*((uint64_t *)ic->arg[1]))
278 #ifdef ALU_S4
279 * 4
280 #endif
281 #ifdef ALU_S8
282 * 8
283 #endif
284 )
285 #ifdef ALU_ADD
286 +
287 #endif
288 #ifdef ALU_SUB
289 -
290 #endif
291 #ifdef ALU_OR
292 |
293 #endif
294 #ifdef ALU_XOR
295 ^
296 #endif
297 #ifdef ALU_AND
298 &
299 #endif
300 #ifdef ALU_SLL
301 <<
302 #endif
303 #if defined(ALU_SRA) || defined(ALU_SRL)
304 >>
305 #endif
306
307 #ifdef ALU_ZAP
308 & zapmask
309 #else /* !ZAP */
310 (
311 #ifdef ALU_NOT
312 ~
313 #endif
314 (
315 #ifdef ALU_IMM
316 (int64_t)ic->arg[2]
317 #else
318 (*((uint64_t *)ic->arg[2]))
319 #endif
320 #if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
321 & 63
322 #endif
323 )
324 )
325 #endif /* !ZAP */
326
327 ;
328
329 #endif /* !ALU_CMP */
330
331 *((uint64_t *)ic->arg[0]) = x;
332 #endif /* ! CMOV */
333 #endif /* ! MSK */
334 #endif /* ! EXT */
335 #endif /* ! INS */
336 }
337

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