/[gxemul]/trunk/src/cpus/cpu_alpha_instr_alu.c
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Contents of /trunk/src/cpus/cpu_alpha_instr_alu.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 6537 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_alpha_instr_alu.c,v 1.4 2006/12/30 13:30:53 debug Exp $
29 *
30 * Alpha ALU instructions. (Included from tmp_alpha_misc.c.)
31 *
32 *
33 * Most ALU instructions have the following arguments:
34 *
35 * arg[0] = pointer to destination uint64_t
36 * arg[1] = pointer to source uint64_t nr 1
37 * arg[2] = pointer to source uint64_t nr 2
38 *
39 * or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
40 *
41 * The main function groups are:
42 *
43 * ALU_INS inserts
44 * ALU_EXT extracts
45 * ALU_MSK masks
46 * ALU_CMOV conditional moves
47 * ALU_CMP compares
48 * ALU_CMPBGE byte compare
49 * none of the above everything else (add, sub, ...)
50 */
51
52 void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
53 {
54 #ifdef ALU_INS
55
56 uint64_t x = *((uint64_t *)ic->arg[1]);
57 int r = (
58 #ifdef ALU_IMM
59 ic->arg[2]
60 #else
61 (*((uint64_t *)ic->arg[2]))
62 #endif
63 & 7) * 8;
64
65 #ifdef ALU_B
66 x &= 0xff;
67 #endif
68 #ifdef ALU_W
69 x &= 0xffff;
70 #endif
71 #ifdef ALU_L
72 x &= 0xffffffffULL;
73 #endif
74
75 #ifdef ALU_LO
76 x <<= r;
77 #else
78 r = 64 - r;
79 if (r == 64)
80 x = 0;
81 else
82 x >>= r;
83 #endif
84 *((uint64_t *)ic->arg[0]) = x;
85
86 #else /* ! INS */
87
88 #ifdef ALU_EXT
89
90 uint64_t x = *((uint64_t *)ic->arg[1]);
91 int r = (
92 #ifdef ALU_IMM
93 ic->arg[2]
94 #else
95 (*((uint64_t *)ic->arg[2]))
96 #endif
97 & 7) * 8;
98 #ifdef ALU_LO
99 x >>= r;
100 #else
101 r = 64 - r;
102 if (r != 64)
103 x <<= r;
104 #endif
105 #ifdef ALU_B
106 x &= 0xff;
107 #endif
108 #ifdef ALU_W
109 x &= 0xffff;
110 #endif
111 #ifdef ALU_L
112 x &= 0xffffffffULL;
113 #endif
114 *((uint64_t *)ic->arg[0]) = x;
115
116 #else /* ! EXT */
117
118 #ifdef ALU_MSK
119
120 uint64_t x = *((uint64_t *)ic->arg[1]);
121 #ifdef ALU_B
122 uint64_t mask = 0x00000000000000ffULL;
123 #endif
124 #ifdef ALU_W
125 uint64_t mask = 0x000000000000ffffULL;
126 #endif
127 #ifdef ALU_L
128 uint64_t mask = 0x00000000ffffffffULL;
129 #endif
130 #ifdef ALU_Q
131 uint64_t mask = 0xffffffffffffffffULL;
132 #endif
133 int r = (
134 #ifdef ALU_IMM
135 ic->arg[2]
136 #else
137 (*((uint64_t *)ic->arg[2]))
138 #endif
139 & 7) * 8;
140
141 #ifdef ALU_LO
142 mask <<= r;
143 #else
144 if (r == 0)
145 mask = 0;
146 else
147 mask >>= (64 - r);
148 #endif
149
150 *((uint64_t *)ic->arg[0]) = x & ~mask;
151
152 #else /* !MSK */
153
154 #ifdef ALU_CMOV
155
156 if (
157 #ifdef ALU_CMOV_lbc
158 !(
159 #endif
160 (*((int64_t *)ic->arg[1]))
161 #ifdef ALU_CMOV_eq
162 == 0
163 #endif
164 #ifdef ALU_CMOV_ne
165 != 0
166 #endif
167 #ifdef ALU_CMOV_le
168 <= 0
169 #endif
170 #ifdef ALU_CMOV_lt
171 < 0
172 #endif
173 #ifdef ALU_CMOV_ge
174 >= 0
175 #endif
176 #ifdef ALU_CMOV_gt
177 > 0
178 #endif
179 #ifdef ALU_CMOV_lbs
180 & 1
181 #endif
182 #ifdef ALU_CMOV_lbc
183 & 1)
184 #endif
185 )
186 *((uint64_t *)ic->arg[0]) =
187 #ifdef ALU_IMM
188 (uint64_t)ic->arg[2]
189 #else
190 (*((uint64_t *)ic->arg[2]))
191 #endif
192 ;
193
194 #else /* ! CMOV */
195
196 #ifdef ALU_CMPBGE
197
198 uint64_t ra = *((uint64_t *)ic->arg[1]), rc = 0, rb =
199 #ifdef ALU_IMM
200 (uint64_t)ic->arg[2]
201 #else
202 (*((uint64_t *)ic->arg[2]))
203 #endif
204 ;
205 int i;
206 for (i=7; i>=0; i--) {
207 if ((uint8_t)ra >= (uint8_t)rb)
208 rc |= (1 << i);
209 rb >>= 8; ra >>= 8;
210 }
211
212 *((uint64_t *)ic->arg[0]) = rc;
213
214 #else /* ! CMPBGE */
215
216 #ifdef ALU_CMP
217
218 uint64_t x;
219
220 x = (*((
221 #ifdef ALU_UNSIGNED
222 uint64_t
223 #else
224 int64_t
225 #endif
226 *)ic->arg[1]))
227
228 #ifdef ALU_CMP_EQ
229 ==
230 #endif
231 #ifdef ALU_CMP_LE
232 <=
233 #endif
234 #ifdef ALU_CMP_LT
235 <
236 #endif
237
238 #ifdef ALU_IMM
239 #ifdef ALU_UNSIGNED
240 (uint64_t)ic->arg[2]
241 #else
242 (int64_t)ic->arg[2]
243 #endif
244 #else
245 #ifdef ALU_UNSIGNED
246 (*((uint64_t *)ic->arg[2]))
247 #else
248 (*((int64_t *)ic->arg[2]))
249 #endif
250 #endif
251 ;
252
253 #else /* !ALU_CMP */
254
255 #ifdef ALU_LONG
256 /* Long */
257 int32_t x;
258 #else
259 /* Quad */
260 int64_t x;
261 #endif
262
263 #ifdef ALU_ZAP
264 /* Prepare for zapping: */
265 uint64_t zapmask = 0xffffffffffffffffULL;
266 int zapbytes =
267 #ifdef ALU_NOT
268 ~
269 #endif
270 #ifdef ALU_IMM
271 (int64_t)ic->arg[2]
272 #else
273 (*((uint64_t *)ic->arg[2]))
274 #endif
275 ;
276 if (zapbytes & 0x80)
277 zapmask &= ~0xff00000000000000ULL;
278 if (zapbytes & 0x40)
279 zapmask &= ~0xff000000000000ULL;
280 if (zapbytes & 0x20)
281 zapmask &= ~0xff0000000000ULL;
282 if (zapbytes & 0x10)
283 zapmask &= ~0xff00000000ULL;
284 if (zapbytes & 0x08)
285 zapmask &= ~0xff000000ULL;
286 if (zapbytes & 0x04)
287 zapmask &= ~0xff0000ULL;
288 if (zapbytes & 0x02)
289 zapmask &= ~0xff00ULL;
290 if (zapbytes & 0x01)
291 zapmask &= ~0xffULL;
292 #endif /* ZAP */
293
294 x = (
295 #ifdef ALU_SRA
296 (int64_t)
297 #endif
298 (*((uint64_t *)ic->arg[1]))
299 #ifdef ALU_S4
300 * 4
301 #endif
302 #ifdef ALU_S8
303 * 8
304 #endif
305 )
306 #ifdef ALU_ADD
307 +
308 #endif
309 #ifdef ALU_SUB
310 -
311 #endif
312 #ifdef ALU_OR
313 |
314 #endif
315 #ifdef ALU_XOR
316 ^
317 #endif
318 #ifdef ALU_AND
319 &
320 #endif
321 #ifdef ALU_SLL
322 <<
323 #endif
324 #if defined(ALU_SRA) || defined(ALU_SRL)
325 >>
326 #endif
327
328 #ifdef ALU_ZAP
329 & zapmask
330 #else /* !ZAP */
331 (
332 #ifdef ALU_NOT
333 ~
334 #endif
335 (
336 #ifdef ALU_IMM
337 (int64_t)ic->arg[2]
338 #else
339 (*((uint64_t *)ic->arg[2]))
340 #endif
341 #if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
342 & 63
343 #endif
344 )
345 )
346 #endif /* !ZAP */
347
348 ;
349
350 #endif /* !ALU_CMP */
351
352 *((uint64_t *)ic->arg[0]) = x;
353 #endif /* ! CMPBGE */
354 #endif /* ! CMOV */
355 #endif /* ! MSK */
356 #endif /* ! EXT */
357 #endif /* ! INS */
358 }
359

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