/[gxemul]/trunk/src/cpus/cpu_alpha_instr_alu.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/cpu_alpha_instr_alu.c

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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 6139 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28     * $Id: cpu_alpha_instr_alu.c,v 1.1 2005/08/29 14:36:41 debug Exp $
29     *
30     * Alpha ALU instructions. (Included from tmp_alpha_misc.c.)
31     *
32     *
33     * Most ALU instructions have the following arguments:
34     *
35     * arg[0] = pointer to destination uint64_t
36     * arg[1] = pointer to source uint64_t nr 1
37     * arg[2] = pointer to source uint64_t nr 2
38     *
39     * or, if ALU_IMM is set, arg[2] contains an 8-bit immediate value.
40     *
41     * The main function groups are:
42     *
43     * ALU_INS inserts
44     * ALU_EXT extracts
45     * ALU_MSK masks
46     * ALU_CMOV conditional moves
47     * ALU_CMP compares
48     * none of the above everything else (add, sub, ...)
49     */
50    
51     void ALU_N(struct cpu *cpu, struct alpha_instr_call *ic)
52     {
53     #ifdef ALU_INS
54    
55     uint64_t x = *((uint64_t *)ic->arg[1]);
56     int r = (
57     #ifdef ALU_IMM
58     ic->arg[2]
59     #else
60     (*((uint64_t *)ic->arg[2]))
61     #endif
62     & 7) * 8;
63    
64     #ifdef ALU_B
65     x &= 0xff;
66     #endif
67     #ifdef ALU_W
68     x &= 0xffff;
69     #endif
70     #ifdef ALU_L
71     x &= 0xffffffffULL;
72     #endif
73    
74     #ifdef ALU_LO
75     x <<= r;
76     #else
77     r = 64 - r;
78     if (r == 64)
79     x = 0;
80     else
81     x >>= r;
82     #endif
83     *((uint64_t *)ic->arg[0]) = x;
84    
85     #else /* ! INS */
86    
87     #ifdef ALU_EXT
88    
89     uint64_t x = *((uint64_t *)ic->arg[1]);
90     int r = (
91     #ifdef ALU_IMM
92     ic->arg[2]
93     #else
94     (*((uint64_t *)ic->arg[2]))
95     #endif
96     & 7) * 8;
97     #ifdef ALU_LO
98     x >>= r;
99     #else
100     r = 64 - r;
101     if (r != 64)
102     x <<= r;
103     #endif
104     #ifdef ALU_B
105     x &= 0xff;
106     #endif
107     #ifdef ALU_W
108     x &= 0xffff;
109     #endif
110     #ifdef ALU_L
111     x &= 0xffffffffULL;
112     #endif
113     *((uint64_t *)ic->arg[0]) = x;
114    
115     #else /* ! EXT */
116    
117     #ifdef ALU_MSK
118    
119     uint64_t x = *((uint64_t *)ic->arg[1]);
120     #ifdef ALU_B
121     uint64_t mask = 0x00000000000000ffULL;
122     #endif
123     #ifdef ALU_W
124     uint64_t mask = 0x000000000000ffffULL;
125     #endif
126     #ifdef ALU_L
127     uint64_t mask = 0x00000000ffffffffULL;
128     #endif
129     #ifdef ALU_Q
130     uint64_t mask = 0xffffffffffffffffULL;
131     #endif
132     int r = (
133     #ifdef ALU_IMM
134     ic->arg[2]
135     #else
136     (*((uint64_t *)ic->arg[2]))
137     #endif
138     & 7) * 8;
139    
140     #ifdef ALU_LO
141     mask <<= r;
142     #else
143     if (r == 0)
144     mask = 0;
145     else
146     mask >>= (64 - r);
147     #endif
148    
149     *((uint64_t *)ic->arg[0]) = x & ~mask;
150    
151     #else /* !MSK */
152    
153     #ifdef ALU_CMOV
154    
155     if (
156     #ifdef ALU_CMOV_lbc
157     !(
158     #endif
159     (*((int64_t *)ic->arg[1]))
160     #ifdef ALU_CMOV_eq
161     == 0
162     #endif
163     #ifdef ALU_CMOV_ne
164     != 0
165     #endif
166     #ifdef ALU_CMOV_le
167     <= 0
168     #endif
169     #ifdef ALU_CMOV_lt
170     < 0
171     #endif
172     #ifdef ALU_CMOV_ge
173     >= 0
174     #endif
175     #ifdef ALU_CMOV_gt
176     > 0
177     #endif
178     #ifdef ALU_CMOV_lbs
179     & 1
180     #endif
181     #ifdef ALU_CMOV_lbc
182     & 1)
183     #endif
184     )
185     *((uint64_t *)ic->arg[0]) =
186     #ifdef ALU_IMM
187     (uint64_t)ic->arg[2]
188     #else
189     (*((uint64_t *)ic->arg[2]))
190     #endif
191     ;
192    
193     #else /* ! CMOV */
194    
195     #ifdef ALU_CMP
196    
197     uint64_t x;
198    
199     x = (*((
200     #ifdef ALU_UNSIGNED
201     uint64_t
202     #else
203     int64_t
204     #endif
205     *)ic->arg[1]))
206    
207     #ifdef ALU_CMP_EQ
208     ==
209     #endif
210     #ifdef ALU_CMP_LE
211     <=
212     #endif
213     #ifdef ALU_CMP_LT
214     <
215     #endif
216    
217     #ifdef ALU_IMM
218     #ifdef ALU_UNSIGNED
219     (uint64_t)ic->arg[2]
220     #else
221     (int64_t)ic->arg[2]
222     #endif
223     #else
224     #ifdef ALU_UNSIGNED
225     (*((uint64_t *)ic->arg[2]))
226     #else
227     (*((int64_t *)ic->arg[2]))
228     #endif
229     #endif
230     ;
231    
232     #else /* !ALU_CMP */
233    
234     #ifdef ALU_LONG
235     /* Long */
236     int32_t x;
237     #else
238     /* Quad */
239     int64_t x;
240     #endif
241    
242     #ifdef ALU_ZAP
243     /* Prepare for zapping: */
244     uint64_t zapmask = 0xffffffffffffffffULL;
245     int zapbytes =
246     #ifdef ALU_NOT
247     ~
248     #endif
249     #ifdef ALU_IMM
250     (int64_t)ic->arg[2]
251     #else
252     (*((uint64_t *)ic->arg[2]))
253     #endif
254     ;
255     if (zapbytes & 0x80)
256     zapmask &= ~0xff00000000000000ULL;
257     if (zapbytes & 0x40)
258     zapmask &= ~0xff000000000000ULL;
259     if (zapbytes & 0x20)
260     zapmask &= ~0xff0000000000ULL;
261     if (zapbytes & 0x10)
262     zapmask &= ~0xff00000000ULL;
263     if (zapbytes & 0x08)
264     zapmask &= ~0xff000000ULL;
265     if (zapbytes & 0x04)
266     zapmask &= ~0xff0000ULL;
267     if (zapbytes & 0x02)
268     zapmask &= ~0xff00ULL;
269     if (zapbytes & 0x01)
270     zapmask &= ~0xffULL;
271     #endif /* ZAP */
272    
273     x = (
274     #ifdef ALU_SRA
275     (int64_t)
276     #endif
277     (*((uint64_t *)ic->arg[1]))
278     #ifdef ALU_S4
279     * 4
280     #endif
281     #ifdef ALU_S8
282     * 8
283     #endif
284     )
285     #ifdef ALU_ADD
286     +
287     #endif
288     #ifdef ALU_SUB
289     -
290     #endif
291     #ifdef ALU_OR
292     |
293     #endif
294     #ifdef ALU_XOR
295     ^
296     #endif
297     #ifdef ALU_AND
298     &
299     #endif
300     #ifdef ALU_SLL
301     <<
302     #endif
303     #if defined(ALU_SRA) || defined(ALU_SRL)
304     >>
305     #endif
306    
307     #ifdef ALU_ZAP
308     & zapmask
309     #else /* !ZAP */
310     (
311     #ifdef ALU_NOT
312     ~
313     #endif
314     (
315     #ifdef ALU_IMM
316     (int64_t)ic->arg[2]
317     #else
318     (*((uint64_t *)ic->arg[2]))
319     #endif
320     #if defined(ALU_SRA) || defined(ALU_SRL) || defined(ALU_SLL)
321     & 63
322     #endif
323     )
324     )
325     #endif /* !ZAP */
326    
327     ;
328    
329     #endif /* !ALU_CMP */
330    
331     *((uint64_t *)ic->arg[0]) = x;
332     #endif /* ! CMOV */
333     #endif /* ! MSK */
334     #endif /* ! EXT */
335     #endif /* ! INS */
336     }
337    

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