/[gxemul]/trunk/src/cpus/cpu_alpha_instr.c
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Annotation of /trunk/src/cpus/cpu_alpha_instr.c

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Revision 44 - (hide annotations)
Mon Oct 8 16:22:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 34252 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.

1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 44 * $Id: cpu_alpha_instr.c,v 1.18 2007/06/28 13:36:46 debug Exp $
29 dpavlin 14 *
30     * Alpha instructions.
31     *
32     * Individual functions should keep track of cpu->n_translated_instrs.
33     * (If no instruction was executed, then it should be decreased. If, say, 4
34     * instructions were combined into one function and executed, then it should
35     * be increased by 3.)
36     */
37    
38    
39 dpavlin 22 #include "float_emul.h"
40    
41    
42 dpavlin 14 /*
43     * nop: Do nothing.
44     */
45     X(nop)
46     {
47     }
48    
49    
50     /*
51     * call_pal: PALcode call
52     *
53     * arg[0] = pal nr
54     */
55     X(call_pal)
56     {
57     /* Synchronize PC first: */
58     uint64_t old_pc, low_pc = ((size_t)ic - (size_t)
59     cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
60     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
61     ALPHA_INSTR_ALIGNMENT_SHIFT);
62     cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
63     old_pc = cpu->pc;
64    
65     alpha_palcode(cpu, ic->arg[0]);
66    
67     if (!cpu->running) {
68     cpu->n_translated_instrs --;
69     cpu->cd.alpha.next_ic = &nothing_call;
70     } else if (cpu->pc != old_pc) {
71     /* The PC value was changed by the palcode call. */
72     /* Find the new physical page and update the translation
73     pointers: */
74     alpha_pc_to_pointers(cpu);
75     }
76     }
77    
78    
79     /*
80     * jsr: Jump to SubRoutine
81     *
82     * arg[0] = ptr to uint64_t where to store return PC
83     * arg[1] = ptr to uint64_t of new PC
84     */
85     X(jsr)
86     {
87     uint64_t old_pc = cpu->pc, low_pc;
88     uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
89     << ALPHA_INSTR_ALIGNMENT_SHIFT) |
90     ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
91    
92     low_pc = ((size_t)ic - (size_t)
93     cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
94     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
95     << ALPHA_INSTR_ALIGNMENT_SHIFT);
96     cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT) + 4;
97    
98     *((int64_t *)ic->arg[0]) = cpu->pc;
99     cpu->pc = *((int64_t *)ic->arg[1]);
100    
101     /*
102     * If this is a jump/return into the same code page as we were
103     * already in, then just set cpu->cd.alpha.next_ic.
104     */
105     if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
106     cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
107     ((cpu->pc & mask_within_page) >> 2);
108     } else {
109     /* Find the new physical page and update pointers: */
110     alpha_pc_to_pointers(cpu);
111     }
112     }
113    
114    
115     /*
116     * jsr_trace: Jump to SubRoutine (with function call trace enabled)
117     *
118     * Arguments same as for jsr.
119     */
120     X(jsr_trace)
121     {
122     cpu_functioncall_trace(cpu, *((int64_t *)ic->arg[1]));
123     instr(jsr)(cpu, ic);
124     }
125    
126    
127     /*
128     * jsr_0: JSR/RET, don't store return PC.
129     *
130     * arg[0] = ignored
131     * arg[1] = ptr to uint64_t of new PC
132     */
133     X(jsr_0)
134     {
135     uint64_t old_pc = cpu->pc;
136     uint64_t mask_within_page = ((ALPHA_IC_ENTRIES_PER_PAGE-1)
137     << ALPHA_INSTR_ALIGNMENT_SHIFT)
138     | ((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
139    
140     cpu->pc = *((int64_t *)ic->arg[1]);
141    
142     /*
143     * If this is a jump/return into the same code page as we were
144     * already in, then just set cpu->cd.alpha.next_ic.
145     */
146     if ((old_pc & ~mask_within_page) == (cpu->pc & ~mask_within_page)) {
147     cpu->cd.alpha.next_ic = cpu->cd.alpha.cur_ic_page +
148     ((cpu->pc & mask_within_page) >> 2);
149     } else {
150     /* Find the new physical page and update pointers: */
151     alpha_pc_to_pointers(cpu);
152     }
153     }
154    
155    
156     /*
157     * jsr_0_trace: JSR/RET (with function call trace enabled)
158     *
159     * Arguments same as for jsr_0.
160     */
161     X(jsr_0_trace)
162     {
163     cpu_functioncall_trace_return(cpu);
164     instr(jsr_0)(cpu, ic);
165     }
166    
167    
168     /*
169     * br: Branch (to a different translated page)
170     *
171     * arg[0] = relative offset (as an int32_t)
172     */
173     X(br)
174     {
175     uint64_t low_pc;
176    
177     /* Calculate new PC from this instruction + arg[0] */
178     low_pc = ((size_t)ic - (size_t)
179     cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
180     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
181     << ALPHA_INSTR_ALIGNMENT_SHIFT);
182     cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
183     cpu->pc += (int32_t)ic->arg[0];
184    
185     /* Find the new physical page and update the translation pointers: */
186     alpha_pc_to_pointers(cpu);
187     }
188    
189    
190     /*
191     * br: Branch (to a different translated page), write return address
192     *
193     * arg[0] = relative offset (as an int32_t)
194     * arg[1] = pointer to uint64_t where to write return address
195     */
196     X(br_return)
197     {
198     uint64_t low_pc;
199    
200     /* Calculate new PC from this instruction + arg[0] */
201     low_pc = ((size_t)ic - (size_t)
202     cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
203     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
204     << ALPHA_INSTR_ALIGNMENT_SHIFT);
205     cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
206    
207     /* ... but first, save away the return address: */
208     *((int64_t *)ic->arg[1]) = cpu->pc + 4;
209    
210     cpu->pc += (int32_t)ic->arg[0];
211    
212     /* Find the new physical page and update the translation pointers: */
213     alpha_pc_to_pointers(cpu);
214     }
215    
216    
217     /*
218     * beq: Branch (to a different translated page) if Equal
219     *
220     * arg[0] = relative offset (as an int32_t)
221     * arg[1] = pointer to int64_t register
222     */
223     X(beq)
224     {
225     if (*((int64_t *)ic->arg[1]) == 0)
226     instr(br)(cpu, ic);
227     }
228    
229    
230     /*
231     * blbs: Branch (to a different translated page) if Low Bit Set
232     *
233     * arg[0] = relative offset (as an int32_t)
234     * arg[1] = pointer to int64_t register
235     */
236     X(blbs)
237     {
238     if (*((int64_t *)ic->arg[1]) & 1)
239     instr(br)(cpu, ic);
240     }
241    
242    
243     /*
244     * blbc: Branch (to a different translated page) if Low Bit Clear
245     *
246     * arg[0] = relative offset (as an int32_t)
247     * arg[1] = pointer to int64_t register
248     */
249     X(blbc)
250     {
251     if (!(*((int64_t *)ic->arg[1]) & 1))
252     instr(br)(cpu, ic);
253     }
254    
255    
256     /*
257     * bne: Branch (to a different translated page) if Not Equal
258     *
259     * arg[0] = relative offset (as an int32_t)
260     * arg[1] = pointer to int64_t register
261     */
262     X(bne)
263     {
264     if (*((int64_t *)ic->arg[1]) != 0)
265     instr(br)(cpu, ic);
266     }
267    
268    
269     /*
270     * ble: Branch (to a different translated page) if Less or Equal
271     *
272     * arg[0] = relative offset (as an int32_t)
273     * arg[1] = pointer to int64_t register
274     */
275     X(ble)
276     {
277     if (*((int64_t *)ic->arg[1]) <= 0)
278     instr(br)(cpu, ic);
279     }
280    
281    
282     /*
283     * blt: Branch (to a different translated page) if Less Than
284     *
285     * arg[0] = relative offset (as an int32_t)
286     * arg[1] = pointer to int64_t register
287     */
288     X(blt)
289     {
290     if (*((int64_t *)ic->arg[1]) < 0)
291     instr(br)(cpu, ic);
292     }
293    
294    
295     /*
296     * bge: Branch (to a different translated page) if Greater or Equal
297     *
298     * arg[0] = relative offset (as an int32_t)
299     * arg[1] = pointer to int64_t register
300     */
301     X(bge)
302     {
303     if (*((int64_t *)ic->arg[1]) >= 0)
304     instr(br)(cpu, ic);
305     }
306    
307    
308     /*
309     * bgt: Branch (to a different translated page) if Greater Than
310     *
311     * arg[0] = relative offset (as an int32_t)
312     * arg[1] = pointer to int64_t register
313     */
314     X(bgt)
315     {
316     if (*((int64_t *)ic->arg[1]) > 0)
317     instr(br)(cpu, ic);
318     }
319    
320    
321     /*
322     * br_samepage: Branch (to within the same translated page)
323     *
324     * arg[0] = pointer to new alpha_instr_call
325     */
326     X(br_samepage)
327     {
328     cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
329     }
330    
331    
332     /*
333     * br_return_samepage: Branch (to within the same translated page),
334     * and save return address
335     *
336     * arg[0] = pointer to new alpha_instr_call
337     * arg[1] = pointer to uint64_t where to store return address
338     */
339     X(br_return_samepage)
340     {
341     uint64_t low_pc;
342    
343     low_pc = ((size_t)ic - (size_t)
344     cpu->cd.alpha.cur_ic_page) / sizeof(struct alpha_instr_call);
345     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
346     << ALPHA_INSTR_ALIGNMENT_SHIFT);
347     cpu->pc += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
348     *((int64_t *)ic->arg[1]) = cpu->pc + 4;
349    
350     cpu->cd.alpha.next_ic = (struct alpha_instr_call *) ic->arg[0];
351     }
352    
353    
354     /*
355     * beq_samepage: Branch (to within the same translated page) if Equal
356     *
357     * arg[0] = pointer to new alpha_instr_call
358     * arg[1] = pointer to int64_t register
359     */
360     X(beq_samepage)
361     {
362     if (*((int64_t *)ic->arg[1]) == 0)
363     instr(br_samepage)(cpu, ic);
364     }
365    
366    
367     /*
368     * blbs_samepage: Branch (to within the same translated page) if Low Bit Set
369     *
370     * arg[0] = pointer to new alpha_instr_call
371     * arg[1] = pointer to int64_t register
372     */
373     X(blbs_samepage)
374     {
375     if (*((int64_t *)ic->arg[1]) & 1)
376     instr(br_samepage)(cpu, ic);
377     }
378    
379    
380     /*
381     * blbc_samepage: Branch (to within the same translated page) if Low Bit Clear
382     *
383     * arg[0] = pointer to new alpha_instr_call
384     * arg[1] = pointer to int64_t register
385     */
386     X(blbc_samepage)
387     {
388     if (!(*((int64_t *)ic->arg[1]) & 1))
389     instr(br_samepage)(cpu, ic);
390     }
391    
392    
393     /*
394     * bne_samepage: Branch (to within the same translated page) if Not Equal
395     *
396     * arg[0] = pointer to new alpha_instr_call
397     * arg[1] = pointer to int64_t register
398     */
399     X(bne_samepage)
400     {
401     if (*((int64_t *)ic->arg[1]) != 0)
402     instr(br_samepage)(cpu, ic);
403     }
404    
405    
406     /*
407     * ble_samepage: Branch (to within the same translated page) if Less or Equal
408     *
409     * arg[0] = pointer to new alpha_instr_call
410     * arg[1] = pointer to int64_t register
411     */
412     X(ble_samepage)
413     {
414     if (*((int64_t *)ic->arg[1]) <= 0)
415     instr(br_samepage)(cpu, ic);
416     }
417    
418    
419     /*
420     * blt_samepage: Branch (to within the same translated page) if Less Than
421     *
422     * arg[0] = pointer to new alpha_instr_call
423     * arg[1] = pointer to int64_t register
424     */
425     X(blt_samepage)
426     {
427     if (*((int64_t *)ic->arg[1]) < 0)
428     instr(br_samepage)(cpu, ic);
429     }
430    
431    
432     /*
433     * bge_samepage: Branch (to within the same translated page)
434     * if Greater or Equal
435     *
436     * arg[0] = pointer to new alpha_instr_call
437     * arg[1] = pointer to int64_t register
438     */
439     X(bge_samepage)
440     {
441     if (*((int64_t *)ic->arg[1]) >= 0)
442     instr(br_samepage)(cpu, ic);
443     }
444    
445    
446     /*
447     * bgt_samepage: Branch (to within the same translated page) if Greater Than
448     *
449     * arg[0] = pointer to new alpha_instr_call
450     * arg[1] = pointer to int64_t register
451     */
452     X(bgt_samepage)
453     {
454     if (*((int64_t *)ic->arg[1]) > 0)
455     instr(br_samepage)(cpu, ic);
456     }
457    
458    
459     /*
460 dpavlin 22 * cvttq/c: Convert floating point to quad.
461     *
462     * arg[0] = pointer to rc (destination integer)
463     * arg[2] = pointer to rb (source float)
464     */
465     X(cvttq_c)
466     {
467     struct ieee_float_value fb;
468     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
469     reg(ic->arg[0]) = fb.nan? 0 : fb.f;
470     }
471    
472    
473     /*
474     * cvtqt: Convert quad to floating point.
475     *
476     * arg[0] = pointer to rc (destination float)
477     * arg[2] = pointer to rb (source quad integer)
478     */
479     X(cvtqt)
480     {
481     reg(ic->arg[0]) = ieee_store_float_value(reg(ic->arg[2]),
482     IEEE_FMT_D, 0);
483     }
484    
485    
486     /*
487     * fabs, fneg: Floating point absolute value, or negation.
488     *
489     * arg[0] = pointer to rc (destination float)
490     * arg[2] = pointer to rb (source quad integer)
491     */
492     X(fabs)
493     {
494     reg(ic->arg[0]) = reg(ic->arg[2]) & 0x7fffffffffffffffULL;
495     }
496     X(fneg)
497     {
498     reg(ic->arg[0]) = reg(ic->arg[2]) ^ 0x8000000000000000ULL;
499     }
500    
501    
502     /*
503     * addt, subt, mult, divt: Floating point arithmetic.
504     *
505     * arg[0] = pointer to rc (destination)
506     * arg[1] = pointer to ra (source)
507     * arg[2] = pointer to rb (source)
508     */
509     X(addt)
510     {
511     struct ieee_float_value fa, fb;
512     double res;
513     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
514     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
515     if (fa.nan | fb.nan)
516     res = 0.0;
517     else
518     res = fa.f + fb.f;
519     reg(ic->arg[0]) = ieee_store_float_value(res,
520     IEEE_FMT_D, fa.nan | fb.nan);
521     }
522     X(subt)
523     {
524     struct ieee_float_value fa, fb;
525     double res;
526     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
527     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
528     if (fa.nan | fb.nan)
529     res = 0.0;
530     else
531     res = fa.f - fb.f;
532     reg(ic->arg[0]) = ieee_store_float_value(res,
533     IEEE_FMT_D, fa.nan | fb.nan);
534     }
535     X(mult)
536     {
537     struct ieee_float_value fa, fb;
538     double res;
539     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
540     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
541     if (fa.nan | fb.nan)
542     res = 0.0;
543     else
544     res = fa.f * fb.f;
545     reg(ic->arg[0]) = ieee_store_float_value(res,
546     IEEE_FMT_D, fa.nan | fb.nan);
547     }
548     X(divt)
549     {
550     struct ieee_float_value fa, fb;
551     double res;
552     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
553     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
554     if (fa.nan | fb.nan || fb.f == 0)
555     res = 0.0;
556     else
557     res = fa.f / fb.f;
558     reg(ic->arg[0]) = ieee_store_float_value(res,
559     IEEE_FMT_D, fa.nan | fb.nan || fb.f == 0);
560     }
561     X(cmpteq)
562     {
563     struct ieee_float_value fa, fb;
564     int res = 0;
565     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
566     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
567     if (fa.nan | fb.nan)
568     res = 0;
569     else
570     res = fa.f == fb.f;
571     reg(ic->arg[0]) = res;
572     }
573     X(cmptlt)
574     {
575     struct ieee_float_value fa, fb;
576     int res = 0;
577     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
578     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
579     if (fa.nan | fb.nan)
580     res = 0;
581     else
582     res = fa.f < fb.f;
583     reg(ic->arg[0]) = res;
584     }
585     X(cmptle)
586     {
587     struct ieee_float_value fa, fb;
588     int res = 0;
589     ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D);
590     ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D);
591     if (fa.nan | fb.nan)
592     res = 0;
593     else
594     res = fa.f <= fb.f;
595     reg(ic->arg[0]) = res;
596     }
597    
598    
599     /*
600 dpavlin 32 * implver: Return CPU implver value.
601     *
602     * arg[0] = pointer to destination uint64_t
603     */
604     X(implver)
605     {
606     reg(ic->arg[0]) = cpu->cd.alpha.cpu_type.implver;
607     }
608    
609    
610     /*
611 dpavlin 14 * mull: Signed Multiply 32x32 => 32.
612     *
613     * arg[0] = pointer to destination uint64_t
614     * arg[1] = pointer to source uint64_t
615     * arg[2] = pointer to source uint64_t
616     */
617     X(mull)
618     {
619     int32_t a = reg(ic->arg[1]);
620     int32_t b = reg(ic->arg[2]);
621     reg(ic->arg[0]) = (int64_t)(int32_t)(a * b);
622     }
623    
624    
625     /*
626     * mulq: Unsigned Multiply 64x64 => 64.
627     *
628     * arg[0] = pointer to destination uint64_t
629     * arg[1] = pointer to source uint64_t
630     * arg[2] = pointer to source uint64_t
631     */
632     X(mulq)
633     {
634     reg(ic->arg[0]) = reg(ic->arg[1]) * reg(ic->arg[2]);
635     }
636    
637    
638     /*
639     * umulh: Unsigned Multiply 64x64 => 128. Store high part in dest reg.
640     *
641     * arg[0] = pointer to destination uint64_t
642     * arg[1] = pointer to source uint64_t
643     * arg[2] = pointer to source uint64_t
644     */
645     X(umulh)
646     {
647     uint64_t reshi = 0, reslo = 0;
648     uint64_t s1 = reg(ic->arg[1]), s2 = reg(ic->arg[2]);
649     int i, bit;
650    
651     for (i=0; i<64; i++) {
652     bit = (s1 & 0x8000000000000000ULL)? 1 : 0;
653     s1 <<= 1;
654    
655     /* If bit in s1 set, then add s2 to reshi/lo: */
656     if (bit) {
657     uint64_t old_reslo = reslo;
658     reslo += s2;
659     if (reslo < old_reslo)
660     reshi ++;
661     }
662    
663     if (i != 63) {
664     reshi <<= 1;
665     reshi += (reslo & 0x8000000000000000ULL? 1 : 0);
666     reslo <<= 1;
667     }
668     }
669    
670     reg(ic->arg[0]) = reshi;
671     }
672    
673    
674     /*
675     * lda: Load address.
676     *
677     * arg[0] = pointer to destination uint64_t
678     * arg[1] = pointer to source uint64_t
679     * arg[2] = offset (possibly as an int32_t)
680     */
681     X(lda)
682     {
683     reg(ic->arg[0]) = reg(ic->arg[1]) + (int64_t)(int32_t)ic->arg[2];
684     }
685    
686    
687     /*
688     * lda_0: Load address compared to the zero register.
689     *
690     * arg[0] = pointer to destination uint64_t
691     * arg[1] = ignored
692     * arg[2] = offset (possibly as an int32_t)
693     */
694     X(lda_0)
695     {
696     reg(ic->arg[0]) = (int64_t)(int32_t)ic->arg[2];
697     }
698    
699    
700     /*
701     * clear: Clear a 64-bit register.
702     *
703     * arg[0] = pointer to destination uint64_t
704     */
705     X(clear)
706     {
707     reg(ic->arg[0]) = 0;
708     }
709    
710    
711     /*
712     * rdcc: Read the Cycle Counter into a 64-bit register.
713     *
714     * arg[0] = pointer to destination uint64_t
715     */
716     X(rdcc)
717     {
718     reg(ic->arg[0]) = cpu->cd.alpha.pcc;
719    
720     /* TODO: actually keep the pcc updated! */
721     cpu->cd.alpha.pcc += 20;
722     }
723    
724    
725     #include "tmp_alpha_misc.c"
726    
727    
728     /*****************************************************************************/
729    
730    
731     X(end_of_page)
732     {
733     /* Update the PC: (offset 0, but on the next page) */
734     cpu->pc &= ~((ALPHA_IC_ENTRIES_PER_PAGE-1)
735     << ALPHA_INSTR_ALIGNMENT_SHIFT);
736     cpu->pc += (ALPHA_IC_ENTRIES_PER_PAGE
737     << ALPHA_INSTR_ALIGNMENT_SHIFT);
738    
739     /* Find the new physical page and update the translation pointers: */
740     alpha_pc_to_pointers(cpu);
741    
742     /* end_of_page doesn't count as an executed instruction: */
743     cpu->n_translated_instrs --;
744     }
745    
746    
747     /*****************************************************************************/
748    
749    
750     /*
751     * alpha_instr_to_be_translated():
752     *
753     * Translate an instruction word into an alpha_instr_call. ic is filled in with
754     * valid data for the translated instruction, or a "nothing" instruction if
755     * there was a translation failure. The newly translated instruction is then
756     * executed.
757     */
758     X(to_be_translated)
759     {
760     uint64_t addr, low_pc;
761     uint32_t iword;
762     unsigned char *page;
763     unsigned char ib[4];
764     void (*samepage_function)(struct cpu *, struct alpha_instr_call *);
765     int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc;
766    
767     /* Figure out the (virtual) address of the instruction: */
768     low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page)
769     / sizeof(struct alpha_instr_call);
770     addr = cpu->pc & ~((ALPHA_IC_ENTRIES_PER_PAGE-1) <<
771     ALPHA_INSTR_ALIGNMENT_SHIFT);
772     addr += (low_pc << ALPHA_INSTR_ALIGNMENT_SHIFT);
773     addr &= ~((1 << ALPHA_INSTR_ALIGNMENT_SHIFT) - 1);
774     cpu->pc = addr;
775    
776     /* Read the instruction word from memory: */
777 dpavlin 24 {
778     const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
779     const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
780     const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
781     uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
782     uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
783     uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
784     DYNTRANS_L3N)) & mask3;
785     struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.alpha.l1_64[x1];
786     struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
787     page = l3->host_load[x3];
788     }
789 dpavlin 14
790     if (page != NULL) {
791     /* fatal("TRANSLATION HIT!\n"); */
792     memcpy(ib, page + (addr & 8191), sizeof(ib));
793     } else {
794     /* fatal("TRANSLATION MISS!\n"); */
795     if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
796     sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
797     fatal("to_be_translated(): read failed: TODO\n");
798     goto bad;
799     }
800     }
801    
802 dpavlin 24 /* Alpha instruction words are always little-endian. Convert
803     to host order: */
804     iword = LE32_TO_HOST( *((uint32_t *)&ib[0]) );
805 dpavlin 14
806    
807     #define DYNTRANS_TO_BE_TRANSLATED_HEAD
808     #include "cpu_dyntrans.c"
809     #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
810    
811    
812     opcode = (iword >> 26) & 63;
813     ra = (iword >> 21) & 31;
814     rb = (iword >> 16) & 31;
815     func = (iword >> 5) & 0x7ff;
816     rc = iword & 31;
817     imm = iword & 0xffff;
818    
819     switch (opcode) {
820     case 0x00: /* CALL_PAL */
821     ic->f = instr(call_pal);
822     ic->arg[0] = (size_t) (iword & 0x3ffffff);
823     break;
824     case 0x08: /* LDA */
825     case 0x09: /* LDAH */
826     if (ra == ALPHA_ZERO) {
827     ic->f = instr(nop);
828     break;
829     }
830     /* TODO: A special case which is common is to add or subtract
831     a small offset from sp. */
832     ic->f = instr(lda);
833     ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
834     ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
835     if (rb == ALPHA_ZERO)
836     ic->f = instr(lda_0);
837     ic->arg[2] = (ssize_t)(int16_t)imm;
838     if (opcode == 0x09)
839     ic->arg[2] <<= 16;
840     break;
841     case 0x0b: /* LDQ_U */
842     case 0x0f: /* STQ_U */
843     if (ra == ALPHA_ZERO && opcode == 0x0b) {
844     ic->f = instr(nop);
845     break;
846     }
847     if (opcode == 0x0b)
848     ic->f = instr(ldq_u);
849     else
850     ic->f = instr(stq_u);
851     ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
852     ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
853     ic->arg[2] = (ssize_t)(int16_t)imm;
854     break;
855     case 0x0a:
856     case 0x0c:
857     case 0x0d:
858     case 0x0e:
859     case 0x22:
860     case 0x23:
861     case 0x26:
862     case 0x27:
863     case 0x28:
864     case 0x29:
865     case 0x2a:
866     case 0x2b:
867     case 0x2c:
868     case 0x2d:
869     case 0x2e:
870     case 0x2f:
871     loadstore_type = 0; fp = 0; load = 0; llsc = 0;
872     switch (opcode) {
873     case 0x0a: loadstore_type = 0; load = 1; break; /* ldbu */
874     case 0x0c: loadstore_type = 1; load = 1; break; /* ldwu */
875     case 0x0d: loadstore_type = 1; break; /* stw */
876     case 0x0e: loadstore_type = 0; break; /* stb */
877     case 0x22: loadstore_type = 2; load = 1; fp = 1; break; /*lds*/
878     case 0x23: loadstore_type = 3; load = 1; fp = 1; break; /*ldt*/
879     case 0x26: loadstore_type = 2; fp = 1; break; /* sts */
880     case 0x27: loadstore_type = 3; fp = 1; break; /* stt */
881     case 0x28: loadstore_type = 2; load = 1; break; /* ldl */
882     case 0x29: loadstore_type = 3; load = 1; break; /* ldq */
883     case 0x2a: loadstore_type = 2; load = llsc = 1; break;/* ldl_l*/
884     case 0x2b: loadstore_type = 3; load = llsc = 1; break;/* ldq_l*/
885     case 0x2c: loadstore_type = 2; break; /* stl */
886     case 0x2d: loadstore_type = 3; break; /* stq */
887     case 0x2e: loadstore_type = 2; llsc = 1; break; /* stl_c */
888     case 0x2f: loadstore_type = 3; llsc = 1; break; /* stq_c */
889     }
890     ic->f = alpha_loadstore[
891     loadstore_type + (imm==0? 4 : 0) + 8 * load
892 dpavlin 28 + 16 * llsc];
893 dpavlin 14 /* Load to the zero register is treated as a prefetch
894     hint. It is ignored here. */
895     if (load && ra == ALPHA_ZERO) {
896     ic->f = instr(nop);
897     break;
898     }
899     if (fp)
900     ic->arg[0] = (size_t) &cpu->cd.alpha.f[ra];
901     else
902     ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
903     ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
904     ic->arg[2] = (ssize_t)(int16_t)imm;
905     break;
906     case 0x10:
907     if (rc == ALPHA_ZERO) {
908     ic->f = instr(nop);
909     break;
910     }
911     ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
912     ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
913     if (func & 0x80)
914     ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
915     else
916     ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
917     switch (func & 0xff) {
918     case 0x00: ic->f = instr(addl); break;
919     case 0x02: ic->f = instr(s4addl); break;
920     case 0x09: ic->f = instr(subl); break;
921     case 0x0b: ic->f = instr(s4subl); break;
922 dpavlin 24 case 0x0f: ic->f = instr(cmpbge); break;
923 dpavlin 14 case 0x12: ic->f = instr(s8addl); break;
924     case 0x1b: ic->f = instr(s8subl); break;
925     case 0x1d: ic->f = instr(cmpult); break;
926     case 0x20: ic->f = instr(addq); break;
927     case 0x22: ic->f = instr(s4addq); break;
928     case 0x29: ic->f = instr(subq); break;
929     case 0x2b: ic->f = instr(s4subq); break;
930     case 0x2d: ic->f = instr(cmpeq); break;
931     case 0x32: ic->f = instr(s8addq); break;
932     case 0x3b: ic->f = instr(s8subq); break;
933     case 0x3d: ic->f = instr(cmpule); break;
934     case 0x4d: ic->f = instr(cmplt); break;
935     case 0x6d: ic->f = instr(cmple); break;
936    
937     case 0x80: ic->f = instr(addl_imm); break;
938     case 0x82: ic->f = instr(s4addl_imm); break;
939     case 0x89: ic->f = instr(subl_imm); break;
940     case 0x8b: ic->f = instr(s4subl_imm); break;
941 dpavlin 24 case 0x8f: ic->f = instr(cmpbge_imm); break;
942 dpavlin 14 case 0x92: ic->f = instr(s8addl_imm); break;
943     case 0x9b: ic->f = instr(s8subl_imm); break;
944     case 0x9d: ic->f = instr(cmpult_imm); break;
945     case 0xa0: ic->f = instr(addq_imm); break;
946     case 0xa2: ic->f = instr(s4addq_imm); break;
947     case 0xa9: ic->f = instr(subq_imm); break;
948     case 0xab: ic->f = instr(s4subq_imm); break;
949     case 0xad: ic->f = instr(cmpeq_imm); break;
950     case 0xb2: ic->f = instr(s8addq_imm); break;
951     case 0xbb: ic->f = instr(s8subq_imm); break;
952     case 0xbd: ic->f = instr(cmpule_imm); break;
953     case 0xcd: ic->f = instr(cmplt_imm); break;
954     case 0xed: ic->f = instr(cmple_imm); break;
955    
956 dpavlin 42 default:if (!cpu->translation_readahead)
957     fatal("[ Alpha: unimplemented function 0x%03x "
958     "for opcode 0x%02x ]\n", func, opcode);
959 dpavlin 14 goto bad;
960     }
961     break;
962     case 0x11:
963     if (rc == ALPHA_ZERO) {
964     ic->f = instr(nop);
965     break;
966     }
967     ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
968     ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
969     if (func & 0x80)
970     ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
971     else
972     ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
973     switch (func & 0xff) {
974     case 0x00: ic->f = instr(and); break;
975     case 0x08: ic->f = instr(andnot); break;
976     case 0x14: ic->f = instr(cmovlbs); break;
977     case 0x16: ic->f = instr(cmovlbc); break;
978     case 0x20: ic->f = instr(or);
979     if (ra == ALPHA_ZERO || rb == ALPHA_ZERO) {
980     if (ra == ALPHA_ZERO)
981     ra = rb;
982     ic->f = alpha_mov_r_r[ra + rc*32];
983     }
984     break;
985     case 0x24: ic->f = instr(cmoveq); break;
986     case 0x26: ic->f = instr(cmovne); break;
987     case 0x28: ic->f = instr(ornot); break;
988     case 0x40: ic->f = instr(xor); break;
989     case 0x44: ic->f = instr(cmovlt); break;
990     case 0x46: ic->f = instr(cmovge); break;
991     case 0x48: ic->f = instr(xornot); break;
992     case 0x64: ic->f = instr(cmovle); break;
993     case 0x66: ic->f = instr(cmovgt); break;
994     case 0x80: ic->f = instr(and_imm); break;
995     case 0x88: ic->f = instr(andnot_imm); break;
996     case 0x94: ic->f = instr(cmovlbs_imm); break;
997     case 0x96: ic->f = instr(cmovlbc_imm); break;
998     case 0xa0: ic->f = instr(or_imm); break;
999     case 0xa4: ic->f = instr(cmoveq_imm); break;
1000     case 0xa6: ic->f = instr(cmovne_imm); break;
1001     case 0xa8: ic->f = instr(ornot_imm); break;
1002     case 0xc0: ic->f = instr(xor_imm); break;
1003     case 0xc4: ic->f = instr(cmovlt_imm); break;
1004     case 0xc6: ic->f = instr(cmovge_imm); break;
1005     case 0xc8: ic->f = instr(xornot_imm); break;
1006     case 0xe4: ic->f = instr(cmovle_imm); break;
1007     case 0xe6: ic->f = instr(cmovgt_imm); break;
1008 dpavlin 32 case 0xec: ic->f = instr(implver); break;
1009 dpavlin 42 default:if (!cpu->translation_readahead)
1010     fatal("[ Alpha: unimplemented function 0x%03x "
1011     "for opcode 0x%02x ]\n", func, opcode);
1012 dpavlin 14 goto bad;
1013     }
1014     break;
1015     case 0x12:
1016     if (rc == ALPHA_ZERO) {
1017     ic->f = instr(nop);
1018     break;
1019     }
1020     ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
1021     ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
1022     if (func & 0x80)
1023     ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
1024     else
1025     ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
1026     switch (func & 0xff) {
1027     case 0x02: ic->f = instr(mskbl); break;
1028     case 0x06: ic->f = instr(extbl); break;
1029     case 0x0b: ic->f = instr(insbl); break;
1030     case 0x12: ic->f = instr(mskwl); break;
1031     case 0x16: ic->f = instr(extwl); break;
1032     case 0x1b: ic->f = instr(inswl); break;
1033     case 0x22: ic->f = instr(mskll); break;
1034     case 0x26: ic->f = instr(extll); break;
1035     case 0x2b: ic->f = instr(insll); break;
1036     case 0x30: ic->f = instr(zap); break;
1037     case 0x31: ic->f = instr(zapnot); break;
1038     case 0x32: ic->f = instr(mskql); break;
1039     case 0x34: ic->f = instr(srl); break;
1040     case 0x36: ic->f = instr(extql); break;
1041     case 0x39: ic->f = instr(sll); break;
1042     case 0x3b: ic->f = instr(insql); break;
1043     case 0x3c: ic->f = instr(sra); break;
1044     case 0x52: ic->f = instr(mskwh); break;
1045     case 0x57: ic->f = instr(inswh); break;
1046     case 0x5a: ic->f = instr(extwh); break;
1047     case 0x62: ic->f = instr(msklh); break;
1048     case 0x67: ic->f = instr(inslh); break;
1049     case 0x6a: ic->f = instr(extlh); break;
1050     case 0x72: ic->f = instr(mskqh); break;
1051     case 0x77: ic->f = instr(insqh); break;
1052     case 0x7a: ic->f = instr(extqh); break;
1053     case 0x82: ic->f = instr(mskbl_imm); break;
1054     case 0x86: ic->f = instr(extbl_imm); break;
1055     case 0x8b: ic->f = instr(insbl_imm); break;
1056     case 0x92: ic->f = instr(mskwl_imm); break;
1057     case 0x96: ic->f = instr(extwl_imm); break;
1058     case 0x9b: ic->f = instr(inswl_imm); break;
1059     case 0xa2: ic->f = instr(mskll_imm); break;
1060     case 0xa6: ic->f = instr(extll_imm); break;
1061     case 0xab: ic->f = instr(insll_imm); break;
1062     case 0xb0: ic->f = instr(zap_imm); break;
1063     case 0xb1: ic->f = instr(zapnot_imm); break;
1064     case 0xb2: ic->f = instr(mskql_imm); break;
1065     case 0xb4: ic->f = instr(srl_imm); break;
1066     case 0xb6: ic->f = instr(extql_imm); break;
1067     case 0xb9: ic->f = instr(sll_imm); break;
1068     case 0xbb: ic->f = instr(insql_imm); break;
1069     case 0xbc: ic->f = instr(sra_imm); break;
1070     case 0xd2: ic->f = instr(mskwh_imm); break;
1071     case 0xd7: ic->f = instr(inswh_imm); break;
1072     case 0xda: ic->f = instr(extwh_imm); break;
1073     case 0xe2: ic->f = instr(msklh_imm); break;
1074     case 0xe7: ic->f = instr(inslh_imm); break;
1075     case 0xea: ic->f = instr(extlh_imm); break;
1076     case 0xf2: ic->f = instr(mskqh_imm); break;
1077     case 0xf7: ic->f = instr(insqh_imm); break;
1078     case 0xfa: ic->f = instr(extqh_imm); break;
1079 dpavlin 42 default:if (!cpu->translation_readahead)
1080     fatal("[ Alpha: unimplemented function 0x%03x "
1081     "for opcode 0x%02x ]\n", func, opcode);
1082 dpavlin 14 goto bad;
1083     }
1084     break;
1085     case 0x13:
1086     if (rc == ALPHA_ZERO) {
1087     ic->f = instr(nop);
1088     break;
1089     }
1090     ic->arg[0] = (size_t) &cpu->cd.alpha.r[rc];
1091     ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
1092     if (func & 0x80)
1093     ic->arg[2] = (size_t)((rb << 3) + (func >> 8));
1094     else
1095     ic->arg[2] = (size_t) &cpu->cd.alpha.r[rb];
1096     switch (func & 0xff) {
1097     case 0x00: ic->f = instr(mull); break;
1098     case 0x20: ic->f = instr(mulq); break;
1099     case 0x30: ic->f = instr(umulh); break;
1100 dpavlin 42 default:if (!cpu->translation_readahead)
1101     fatal("[ Alpha: unimplemented function 0x%03x "
1102     "for opcode 0x%02x ]\n", func, opcode);
1103 dpavlin 14 goto bad;
1104     }
1105     break;
1106     case 0x16:
1107     if (rc == ALPHA_ZERO) {
1108     ic->f = instr(nop);
1109     break;
1110     }
1111     ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
1112     ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
1113     ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
1114     switch (func & 0x7ff) {
1115 dpavlin 22 case 0x02f: ic->f = instr(cvttq_c); break;
1116     case 0x0a0: ic->f = instr(addt); break;
1117     case 0x0a1: ic->f = instr(subt); break;
1118     case 0x0a2: ic->f = instr(mult); break;
1119     case 0x0a3: ic->f = instr(divt); break;
1120     case 0x0a5: ic->f = instr(cmpteq); break;
1121     case 0x0a6: ic->f = instr(cmptlt); break;
1122     case 0x0a7: ic->f = instr(cmptle); break;
1123     case 0x0be: ic->f = instr(cvtqt); break;
1124 dpavlin 42 default:if (!cpu->translation_readahead)
1125     fatal("[ Alpha: unimplemented function 0x%03x "
1126     "for opcode 0x%02x ]\n", func, opcode);
1127 dpavlin 14 goto bad;
1128     }
1129     break;
1130     case 0x17:
1131     if (rc == ALPHA_ZERO) {
1132     ic->f = instr(nop);
1133     break;
1134     }
1135     ic->arg[0] = (size_t) &cpu->cd.alpha.f[rc];
1136     ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
1137     ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb];
1138     switch (func & 0x7ff) {
1139     case 0x020:
1140 dpavlin 22 /* fabs (or fclr): */
1141 dpavlin 14 if (ra == 31 && rb == 31)
1142     ic->f = instr(clear);
1143 dpavlin 22 else
1144     ic->f = instr(fabs);
1145 dpavlin 14 break;
1146 dpavlin 22 case 0x021:
1147     ic->f = instr(fneg);
1148     break;
1149 dpavlin 42 default:if (!cpu->translation_readahead)
1150     fatal("[ Alpha: unimplemented function 0x%03x "
1151     "for opcode 0x%02x ]\n", func, opcode);
1152 dpavlin 14 goto bad;
1153     }
1154     break;
1155     case 0x18:
1156     switch (iword & 0xffff) {
1157     case 0x4000: /* mb */
1158     case 0x4400: /* wmb */
1159     ic->f = instr(nop);
1160     break;
1161     case 0xc000: /* rdcc ra */
1162     if (ra == ALPHA_ZERO) {
1163     ic->f = instr(nop);
1164     break;
1165     }
1166     ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
1167     ic->f = instr(rdcc);
1168     break;
1169 dpavlin 42 default:if (!cpu->translation_readahead)
1170     fatal("[ Alpha: unimplemented function 0x%03x "
1171     "for opcode 0x%02x ]\n", func, opcode);
1172 dpavlin 14 goto bad;
1173     }
1174     break;
1175     case 0x1a:
1176     switch ((iword >> 14) & 3) {
1177     case 0: /* JMP */
1178     case 1: /* JSR */
1179     case 2: /* RET */
1180     ic->arg[0] = (size_t) &cpu->cd.alpha.r[ra];
1181     ic->arg[1] = (size_t) &cpu->cd.alpha.r[rb];
1182     if (ra == ALPHA_ZERO) {
1183     if (cpu->machine->show_trace_tree &&
1184     rb == ALPHA_RA)
1185     ic->f = instr(jsr_0_trace);
1186     else
1187     ic->f = instr(jsr_0);
1188     } else {
1189     if (cpu->machine->show_trace_tree)
1190     ic->f = instr(jsr_trace);
1191     else
1192     ic->f = instr(jsr);
1193     }
1194     break;
1195 dpavlin 42 default:if (!cpu->translation_readahead)
1196     fatal("[ Alpha: unimpl JSR type %i, ra=%i "
1197     "rb=%i ]\n", ((iword >> 14) & 3), ra, rb);
1198 dpavlin 14 goto bad;
1199     }
1200     break;
1201 dpavlin 22 case 0x30: /* BR */
1202     case 0x31: /* FBEQ */
1203     case 0x34: /* BSR */
1204     case 0x35: /* FBNE */
1205 dpavlin 14 case 0x38: /* BLBC */
1206 dpavlin 22 case 0x39: /* BEQ */
1207     case 0x3a: /* BLT */
1208     case 0x3b: /* BLE */
1209 dpavlin 14 case 0x3c: /* BLBS */
1210 dpavlin 22 case 0x3d: /* BNE */
1211     case 0x3e: /* BGE */
1212     case 0x3f: /* BGT */
1213 dpavlin 14 /* To avoid a GCC warning: */
1214     samepage_function = instr(nop);
1215 dpavlin 22 fp = 0;
1216 dpavlin 14 switch (opcode) {
1217     case 0x30:
1218     case 0x34:
1219     ic->f = instr(br);
1220     samepage_function = instr(br_samepage);
1221     if (ra != ALPHA_ZERO) {
1222     ic->f = instr(br_return);
1223     samepage_function = instr(br_return_samepage);
1224     }
1225     break;
1226     case 0x38:
1227     ic->f = instr(blbc);
1228     samepage_function = instr(blbc_samepage);
1229     break;
1230 dpavlin 22 case 0x31:
1231     fp = 1;
1232 dpavlin 14 case 0x39:
1233     ic->f = instr(beq);
1234     samepage_function = instr(beq_samepage);
1235     break;
1236     case 0x3a:
1237     ic->f = instr(blt);
1238     samepage_function = instr(blt_samepage);
1239     break;
1240     case 0x3b:
1241     ic->f = instr(ble);
1242     samepage_function = instr(ble_samepage);
1243     break;
1244     case 0x3c:
1245     ic->f = instr(blbs);
1246     samepage_function = instr(blbs_samepage);
1247     break;
1248 dpavlin 22 case 0x35:
1249     fp = 1;
1250 dpavlin 14 case 0x3d:
1251     ic->f = instr(bne);
1252     samepage_function = instr(bne_samepage);
1253     break;
1254     case 0x3e:
1255     ic->f = instr(bge);
1256     samepage_function = instr(bge_samepage);
1257     break;
1258     case 0x3f:
1259     ic->f = instr(bgt);
1260     samepage_function = instr(bgt_samepage);
1261     break;
1262     }
1263 dpavlin 22 if (fp)
1264     ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra];
1265     else
1266     ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra];
1267 dpavlin 14 ic->arg[0] = (iword & 0x001fffff) << 2;
1268     /* Sign-extend: */
1269     if (ic->arg[0] & 0x00400000)
1270     ic->arg[0] |= 0xffffffffff800000ULL;
1271     /* Branches are calculated as PC + 4 + offset. */
1272     ic->arg[0] = (size_t)(ic->arg[0] + 4);
1273     /* Special case: branch within the same page: */
1274     {
1275     uint64_t mask_within_page =
1276     ((ALPHA_IC_ENTRIES_PER_PAGE-1) << 2) | 3;
1277     uint64_t old_pc = addr;
1278     uint64_t new_pc = old_pc + (int32_t)ic->arg[0];
1279     if ((old_pc & ~mask_within_page) ==
1280     (new_pc & ~mask_within_page)) {
1281     ic->f = samepage_function;
1282     ic->arg[0] = (size_t) (
1283     cpu->cd.alpha.cur_ic_page +
1284     ((new_pc & mask_within_page) >> 2));
1285     }
1286     }
1287     break;
1288 dpavlin 42 default:if (!cpu->translation_readahead)
1289     fatal("[ UNIMPLEMENTED Alpha opcode 0x%x ]\n", opcode);
1290 dpavlin 14 goto bad;
1291     }
1292    
1293    
1294     #define DYNTRANS_TO_BE_TRANSLATED_TAIL
1295     #include "cpu_dyntrans.c"
1296     #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
1297     }
1298    

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