/[gxemul]/trunk/src/cpus/cpu_alpha_instr.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/cpus/cpu_alpha_instr.c

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: cpu_alpha_instr.c,v 1.7 2006/02/09 22:40:27 debug Exp $   *  $Id: cpu_alpha_instr.c,v 1.11 2006/06/03 06:46:44 debug Exp $
29   *   *
30   *  Alpha instructions.   *  Alpha instructions.
31   *   *
# Line 749  X(to_be_translated) Line 749  X(to_be_translated)
749  {  {
750          uint64_t addr, low_pc;          uint64_t addr, low_pc;
751          uint32_t iword;          uint32_t iword;
         struct alpha_vph_page *vph_p;  
752          unsigned char *page;          unsigned char *page;
753          unsigned char ib[4];          unsigned char ib[4];
754          void (*samepage_function)(struct cpu *, struct alpha_instr_call *);          void (*samepage_function)(struct cpu *, struct alpha_instr_call *);
755          int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc;          int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc;
 #ifdef DYNTRANS_BACKEND  
         int simple = 0;  
 #endif  
756    
757          /*  Figure out the (virtual) address of the instruction:  */          /*  Figure out the (virtual) address of the instruction:  */
758          low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page)          low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page)
# Line 768  X(to_be_translated) Line 764  X(to_be_translated)
764          cpu->pc = addr;          cpu->pc = addr;
765    
766          /*  Read the instruction word from memory:  */          /*  Read the instruction word from memory:  */
767          if ((addr >> ALPHA_TOPSHIFT) == 0) {          {
768                  vph_p = cpu->cd.alpha.vph_table0[(addr >>                  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
769                      ALPHA_LEVEL0_SHIFT) & 8191];                  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
770                  page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];                  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
771          } else if ((addr >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) {                  uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
772                  vph_p = cpu->cd.alpha.vph_table0_kernel[(addr >>                  uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
773                      ALPHA_LEVEL0_SHIFT) & 8191];                  uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
774                  page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];                      DYNTRANS_L3N)) & mask3;
775          } else                  struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.alpha.l1_64[x1];
776                  page = NULL;                  struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
777                    page = l3->host_load[x3];
778            }
779    
780          if (page != NULL) {          if (page != NULL) {
781                  /*  fatal("TRANSLATION HIT!\n");  */                  /*  fatal("TRANSLATION HIT!\n");  */
# Line 791  X(to_be_translated) Line 789  X(to_be_translated)
789                  }                  }
790          }          }
791    
792  #ifdef HOST_LITTLE_ENDIAN          /*  Alpha instruction words are always little-endian. Convert
793          iword = *((uint32_t *)&ib[0]);              to host order:  */
794  #else          iword = LE32_TO_HOST( *((uint32_t *)&ib[0]) );
         iword = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);  
 #endif  
   
         /*  fatal("{ Alpha: translating pc=0x%016llx iword=0x%08x }\n",  
             (long long)addr, (int)iword);  */  
795    
796    
797  #define DYNTRANS_TO_BE_TRANSLATED_HEAD  #define DYNTRANS_TO_BE_TRANSLATED_HEAD
# Line 917  X(to_be_translated) Line 910  X(to_be_translated)
910                  case 0x02: ic->f = instr(s4addl); break;                  case 0x02: ic->f = instr(s4addl); break;
911                  case 0x09: ic->f = instr(subl); break;                  case 0x09: ic->f = instr(subl); break;
912                  case 0x0b: ic->f = instr(s4subl); break;                  case 0x0b: ic->f = instr(s4subl); break;
913                    case 0x0f: ic->f = instr(cmpbge); break;
914                  case 0x12: ic->f = instr(s8addl); break;                  case 0x12: ic->f = instr(s8addl); break;
915                  case 0x1b: ic->f = instr(s8subl); break;                  case 0x1b: ic->f = instr(s8subl); break;
916                  case 0x1d: ic->f = instr(cmpult); break;                  case 0x1d: ic->f = instr(cmpult); break;
# Line 935  X(to_be_translated) Line 929  X(to_be_translated)
929                  case 0x82: ic->f = instr(s4addl_imm); break;                  case 0x82: ic->f = instr(s4addl_imm); break;
930                  case 0x89: ic->f = instr(subl_imm); break;                  case 0x89: ic->f = instr(subl_imm); break;
931                  case 0x8b: ic->f = instr(s4subl_imm); break;                  case 0x8b: ic->f = instr(s4subl_imm); break;
932                    case 0x8f: ic->f = instr(cmpbge_imm); break;
933                  case 0x92: ic->f = instr(s8addl_imm); break;                  case 0x92: ic->f = instr(s8addl_imm); break;
934                  case 0x9b: ic->f = instr(s8subl_imm); break;                  case 0x9b: ic->f = instr(s8subl_imm); break;
935                  case 0x9d: ic->f = instr(cmpult_imm); break;                  case 0x9d: ic->f = instr(cmpult_imm); break;
Legend:
Removed from v.22  
changed lines
  Added in v.24
  ViewVC Help
Powered by ViewVC 1.1.26