1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_alpha_instr.c,v 1.2 2005/09/17 17:14:27 debug Exp $ |
* $Id: cpu_alpha_instr.c,v 1.13 2006/07/26 23:21:47 debug Exp $ |
29 |
* |
* |
30 |
* Alpha instructions. |
* Alpha instructions. |
31 |
* |
* |
36 |
*/ |
*/ |
37 |
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38 |
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39 |
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#include "float_emul.h" |
40 |
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41 |
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42 |
/* |
/* |
43 |
* nop: Do nothing. |
* nop: Do nothing. |
44 |
*/ |
*/ |
65 |
alpha_palcode(cpu, ic->arg[0]); |
alpha_palcode(cpu, ic->arg[0]); |
66 |
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|
67 |
if (!cpu->running) { |
if (!cpu->running) { |
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cpu->running_translated = 0; |
|
68 |
cpu->n_translated_instrs --; |
cpu->n_translated_instrs --; |
69 |
cpu->cd.alpha.next_ic = ¬hing_call; |
cpu->cd.alpha.next_ic = ¬hing_call; |
70 |
} else if (cpu->pc != old_pc) { |
} else if (cpu->pc != old_pc) { |
457 |
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458 |
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459 |
/* |
/* |
460 |
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* cvttq/c: Convert floating point to quad. |
461 |
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* |
462 |
|
* arg[0] = pointer to rc (destination integer) |
463 |
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* arg[2] = pointer to rb (source float) |
464 |
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*/ |
465 |
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X(cvttq_c) |
466 |
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{ |
467 |
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struct ieee_float_value fb; |
468 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
469 |
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reg(ic->arg[0]) = fb.nan? 0 : fb.f; |
470 |
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} |
471 |
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472 |
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473 |
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/* |
474 |
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* cvtqt: Convert quad to floating point. |
475 |
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* |
476 |
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* arg[0] = pointer to rc (destination float) |
477 |
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* arg[2] = pointer to rb (source quad integer) |
478 |
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*/ |
479 |
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X(cvtqt) |
480 |
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{ |
481 |
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reg(ic->arg[0]) = ieee_store_float_value(reg(ic->arg[2]), |
482 |
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IEEE_FMT_D, 0); |
483 |
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} |
484 |
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485 |
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|
486 |
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/* |
487 |
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* fabs, fneg: Floating point absolute value, or negation. |
488 |
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* |
489 |
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* arg[0] = pointer to rc (destination float) |
490 |
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* arg[2] = pointer to rb (source quad integer) |
491 |
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*/ |
492 |
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X(fabs) |
493 |
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{ |
494 |
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reg(ic->arg[0]) = reg(ic->arg[2]) & 0x7fffffffffffffffULL; |
495 |
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} |
496 |
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X(fneg) |
497 |
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{ |
498 |
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reg(ic->arg[0]) = reg(ic->arg[2]) ^ 0x8000000000000000ULL; |
499 |
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} |
500 |
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501 |
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502 |
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/* |
503 |
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* addt, subt, mult, divt: Floating point arithmetic. |
504 |
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* |
505 |
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* arg[0] = pointer to rc (destination) |
506 |
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* arg[1] = pointer to ra (source) |
507 |
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* arg[2] = pointer to rb (source) |
508 |
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*/ |
509 |
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X(addt) |
510 |
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{ |
511 |
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struct ieee_float_value fa, fb; |
512 |
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double res; |
513 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
514 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
515 |
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if (fa.nan | fb.nan) |
516 |
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res = 0.0; |
517 |
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else |
518 |
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res = fa.f + fb.f; |
519 |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
520 |
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IEEE_FMT_D, fa.nan | fb.nan); |
521 |
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} |
522 |
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X(subt) |
523 |
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{ |
524 |
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struct ieee_float_value fa, fb; |
525 |
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double res; |
526 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
527 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
528 |
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if (fa.nan | fb.nan) |
529 |
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res = 0.0; |
530 |
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else |
531 |
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res = fa.f - fb.f; |
532 |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
533 |
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IEEE_FMT_D, fa.nan | fb.nan); |
534 |
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} |
535 |
|
X(mult) |
536 |
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{ |
537 |
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struct ieee_float_value fa, fb; |
538 |
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double res; |
539 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
540 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
541 |
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if (fa.nan | fb.nan) |
542 |
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res = 0.0; |
543 |
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else |
544 |
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res = fa.f * fb.f; |
545 |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
546 |
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IEEE_FMT_D, fa.nan | fb.nan); |
547 |
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} |
548 |
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X(divt) |
549 |
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{ |
550 |
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struct ieee_float_value fa, fb; |
551 |
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double res; |
552 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
553 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
554 |
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if (fa.nan | fb.nan || fb.f == 0) |
555 |
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res = 0.0; |
556 |
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else |
557 |
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res = fa.f / fb.f; |
558 |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
559 |
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IEEE_FMT_D, fa.nan | fb.nan || fb.f == 0); |
560 |
|
} |
561 |
|
X(cmpteq) |
562 |
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{ |
563 |
|
struct ieee_float_value fa, fb; |
564 |
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int res = 0; |
565 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
566 |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
567 |
|
if (fa.nan | fb.nan) |
568 |
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res = 0; |
569 |
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else |
570 |
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res = fa.f == fb.f; |
571 |
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reg(ic->arg[0]) = res; |
572 |
|
} |
573 |
|
X(cmptlt) |
574 |
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{ |
575 |
|
struct ieee_float_value fa, fb; |
576 |
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int res = 0; |
577 |
|
ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
578 |
|
ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
579 |
|
if (fa.nan | fb.nan) |
580 |
|
res = 0; |
581 |
|
else |
582 |
|
res = fa.f < fb.f; |
583 |
|
reg(ic->arg[0]) = res; |
584 |
|
} |
585 |
|
X(cmptle) |
586 |
|
{ |
587 |
|
struct ieee_float_value fa, fb; |
588 |
|
int res = 0; |
589 |
|
ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
590 |
|
ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
591 |
|
if (fa.nan | fb.nan) |
592 |
|
res = 0; |
593 |
|
else |
594 |
|
res = fa.f <= fb.f; |
595 |
|
reg(ic->arg[0]) = res; |
596 |
|
} |
597 |
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|
598 |
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|
599 |
|
/* |
600 |
* mull: Signed Multiply 32x32 => 32. |
* mull: Signed Multiply 32x32 => 32. |
601 |
* |
* |
602 |
* arg[0] = pointer to destination uint64_t |
* arg[0] = pointer to destination uint64_t |
737 |
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738 |
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739 |
/* |
/* |
|
* alpha_combine_instructions(): |
|
|
* |
|
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* Combine two or more instructions, if possible, into a single function call. |
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*/ |
|
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void alpha_combine_instructions(struct cpu *cpu, struct alpha_instr_call *ic, |
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uint64_t addr) |
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{ |
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int n_back; |
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n_back = (addr >> 2) & (ALPHA_IC_ENTRIES_PER_PAGE-1); |
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if (n_back >= 1) { |
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} |
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/* TODO: Combine forward as well */ |
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} |
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/*****************************************************************************/ |
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/* |
|
740 |
* alpha_instr_to_be_translated(): |
* alpha_instr_to_be_translated(): |
741 |
* |
* |
742 |
* Translate an instruction word into an alpha_instr_call. ic is filled in with |
* Translate an instruction word into an alpha_instr_call. ic is filled in with |
748 |
{ |
{ |
749 |
uint64_t addr, low_pc; |
uint64_t addr, low_pc; |
750 |
uint32_t iword; |
uint32_t iword; |
|
struct alpha_vph_page *vph_p; |
|
751 |
unsigned char *page; |
unsigned char *page; |
752 |
unsigned char ib[4]; |
unsigned char ib[4]; |
753 |
void (*samepage_function)(struct cpu *, struct alpha_instr_call *); |
void (*samepage_function)(struct cpu *, struct alpha_instr_call *); |
763 |
cpu->pc = addr; |
cpu->pc = addr; |
764 |
|
|
765 |
/* Read the instruction word from memory: */ |
/* Read the instruction word from memory: */ |
766 |
if ((addr >> ALPHA_TOPSHIFT) == 0) { |
{ |
767 |
vph_p = cpu->cd.alpha.vph_table0[(addr >> |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
768 |
ALPHA_LEVEL0_SHIFT) & 8191]; |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
769 |
page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191]; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
770 |
} else if ((addr >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1; |
771 |
vph_p = cpu->cd.alpha.vph_table0_kernel[(addr >> |
uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
772 |
ALPHA_LEVEL0_SHIFT) & 8191]; |
uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N- |
773 |
page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191]; |
DYNTRANS_L3N)) & mask3; |
774 |
} else |
struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.alpha.l1_64[x1]; |
775 |
page = NULL; |
struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2]; |
776 |
|
page = l3->host_load[x3]; |
777 |
|
} |
778 |
|
|
779 |
if (page != NULL) { |
if (page != NULL) { |
780 |
/* fatal("TRANSLATION HIT!\n"); */ |
/* fatal("TRANSLATION HIT!\n"); */ |
788 |
} |
} |
789 |
} |
} |
790 |
|
|
791 |
#ifdef HOST_LITTLE_ENDIAN |
/* Alpha instruction words are always little-endian. Convert |
792 |
iword = *((uint32_t *)&ib[0]); |
to host order: */ |
793 |
#else |
iword = LE32_TO_HOST( *((uint32_t *)&ib[0]) ); |
|
iword = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
|
|
#endif |
|
|
|
|
|
/* fatal("{ Alpha: translating pc=0x%016llx iword=0x%08x }\n", |
|
|
(long long)addr, (int)iword); */ |
|
794 |
|
|
795 |
|
|
796 |
#define DYNTRANS_TO_BE_TRANSLATED_HEAD |
#define DYNTRANS_TO_BE_TRANSLATED_HEAD |
878 |
} |
} |
879 |
ic->f = alpha_loadstore[ |
ic->f = alpha_loadstore[ |
880 |
loadstore_type + (imm==0? 4 : 0) + 8 * load |
loadstore_type + (imm==0? 4 : 0) + 8 * load |
881 |
+ (cpu->machine->dyntrans_alignment_check? 16:0) |
+ 16 * llsc]; |
|
+ 32 * llsc]; |
|
882 |
/* Load to the zero register is treated as a prefetch |
/* Load to the zero register is treated as a prefetch |
883 |
hint. It is ignored here. */ |
hint. It is ignored here. */ |
884 |
if (load && ra == ALPHA_ZERO) { |
if (load && ra == ALPHA_ZERO) { |
908 |
case 0x02: ic->f = instr(s4addl); break; |
case 0x02: ic->f = instr(s4addl); break; |
909 |
case 0x09: ic->f = instr(subl); break; |
case 0x09: ic->f = instr(subl); break; |
910 |
case 0x0b: ic->f = instr(s4subl); break; |
case 0x0b: ic->f = instr(s4subl); break; |
911 |
|
case 0x0f: ic->f = instr(cmpbge); break; |
912 |
case 0x12: ic->f = instr(s8addl); break; |
case 0x12: ic->f = instr(s8addl); break; |
913 |
case 0x1b: ic->f = instr(s8subl); break; |
case 0x1b: ic->f = instr(s8subl); break; |
914 |
case 0x1d: ic->f = instr(cmpult); break; |
case 0x1d: ic->f = instr(cmpult); break; |
927 |
case 0x82: ic->f = instr(s4addl_imm); break; |
case 0x82: ic->f = instr(s4addl_imm); break; |
928 |
case 0x89: ic->f = instr(subl_imm); break; |
case 0x89: ic->f = instr(subl_imm); break; |
929 |
case 0x8b: ic->f = instr(s4subl_imm); break; |
case 0x8b: ic->f = instr(s4subl_imm); break; |
930 |
|
case 0x8f: ic->f = instr(cmpbge_imm); break; |
931 |
case 0x92: ic->f = instr(s8addl_imm); break; |
case 0x92: ic->f = instr(s8addl_imm); break; |
932 |
case 0x9b: ic->f = instr(s8subl_imm); break; |
case 0x9b: ic->f = instr(s8subl_imm); break; |
933 |
case 0x9d: ic->f = instr(cmpult_imm); break; |
case 0x9d: ic->f = instr(cmpult_imm); break; |
1096 |
ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
1097 |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
1098 |
switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
1099 |
|
case 0x02f: ic->f = instr(cvttq_c); break; |
1100 |
|
case 0x0a0: ic->f = instr(addt); break; |
1101 |
|
case 0x0a1: ic->f = instr(subt); break; |
1102 |
|
case 0x0a2: ic->f = instr(mult); break; |
1103 |
|
case 0x0a3: ic->f = instr(divt); break; |
1104 |
|
case 0x0a5: ic->f = instr(cmpteq); break; |
1105 |
|
case 0x0a6: ic->f = instr(cmptlt); break; |
1106 |
|
case 0x0a7: ic->f = instr(cmptle); break; |
1107 |
|
case 0x0be: ic->f = instr(cvtqt); break; |
1108 |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
1109 |
" opcode 0x%02x ]\n", func, opcode); |
" opcode 0x%02x ]\n", func, opcode); |
1110 |
goto bad; |
goto bad; |
1120 |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
1121 |
switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
1122 |
case 0x020: |
case 0x020: |
1123 |
/* fclr: */ |
/* fabs (or fclr): */ |
1124 |
if (ra == 31 && rb == 31) |
if (ra == 31 && rb == 31) |
1125 |
ic->f = instr(clear); |
ic->f = instr(clear); |
1126 |
else { |
else |
1127 |
/* fabs: */ |
ic->f = instr(fabs); |
1128 |
goto bad; |
break; |
1129 |
} |
case 0x021: |
1130 |
|
ic->f = instr(fneg); |
1131 |
break; |
break; |
1132 |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
1133 |
" opcode 0x%02x ]\n", func, opcode); |
" opcode 0x%02x ]\n", func, opcode); |
1178 |
goto bad; |
goto bad; |
1179 |
} |
} |
1180 |
break; |
break; |
1181 |
case 0x30: /* BR */ |
case 0x30: /* BR */ |
1182 |
case 0x34: /* BSR */ |
case 0x31: /* FBEQ */ |
1183 |
|
case 0x34: /* BSR */ |
1184 |
|
case 0x35: /* FBNE */ |
1185 |
case 0x38: /* BLBC */ |
case 0x38: /* BLBC */ |
1186 |
case 0x39: /* BEQ */ |
case 0x39: /* BEQ */ |
1187 |
case 0x3a: /* BLT */ |
case 0x3a: /* BLT */ |
1188 |
case 0x3b: /* BLE */ |
case 0x3b: /* BLE */ |
1189 |
case 0x3c: /* BLBS */ |
case 0x3c: /* BLBS */ |
1190 |
case 0x3d: /* BNE */ |
case 0x3d: /* BNE */ |
1191 |
case 0x3e: /* BGE */ |
case 0x3e: /* BGE */ |
1192 |
case 0x3f: /* BGT */ |
case 0x3f: /* BGT */ |
1193 |
/* To avoid a GCC warning: */ |
/* To avoid a GCC warning: */ |
1194 |
samepage_function = instr(nop); |
samepage_function = instr(nop); |
1195 |
|
fp = 0; |
1196 |
switch (opcode) { |
switch (opcode) { |
1197 |
case 0x30: |
case 0x30: |
1198 |
case 0x34: |
case 0x34: |
1207 |
ic->f = instr(blbc); |
ic->f = instr(blbc); |
1208 |
samepage_function = instr(blbc_samepage); |
samepage_function = instr(blbc_samepage); |
1209 |
break; |
break; |
1210 |
|
case 0x31: |
1211 |
|
fp = 1; |
1212 |
case 0x39: |
case 0x39: |
1213 |
ic->f = instr(beq); |
ic->f = instr(beq); |
1214 |
samepage_function = instr(beq_samepage); |
samepage_function = instr(beq_samepage); |
1225 |
ic->f = instr(blbs); |
ic->f = instr(blbs); |
1226 |
samepage_function = instr(blbs_samepage); |
samepage_function = instr(blbs_samepage); |
1227 |
break; |
break; |
1228 |
|
case 0x35: |
1229 |
|
fp = 1; |
1230 |
case 0x3d: |
case 0x3d: |
1231 |
ic->f = instr(bne); |
ic->f = instr(bne); |
1232 |
samepage_function = instr(bne_samepage); |
samepage_function = instr(bne_samepage); |
1240 |
samepage_function = instr(bgt_samepage); |
samepage_function = instr(bgt_samepage); |
1241 |
break; |
break; |
1242 |
} |
} |
1243 |
ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra]; |
if (fp) |
1244 |
|
ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
1245 |
|
else |
1246 |
|
ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra]; |
1247 |
ic->arg[0] = (iword & 0x001fffff) << 2; |
ic->arg[0] = (iword & 0x001fffff) << 2; |
1248 |
/* Sign-extend: */ |
/* Sign-extend: */ |
1249 |
if (ic->arg[0] & 0x00400000) |
if (ic->arg[0] & 0x00400000) |