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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_alpha.c,v 1.1 2005/08/29 14:36:41 debug Exp $ |
* $Id: cpu_alpha.c,v 1.27 2007/06/07 15:36:24 debug Exp $ |
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* |
* |
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* Alpha CPU emulation. |
* Alpha CPU emulation. |
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* |
* |
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#include <ctype.h> |
#include <ctype.h> |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
46 |
#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#include "timer.h" |
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#define DYNTRANS_8K |
#define DYNTRANS_8K |
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#define DYNTRANS_PAGESIZE 8192 |
#define DYNTRANS_PAGESIZE 8192 |
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#include "tmp_alpha_head.c" |
#include "tmp_alpha_head.c" |
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extern int native_code_translation_enabled; |
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/* Alpha symbolic register names: */ |
/* Alpha symbolic register names: */ |
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static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
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void alpha_irq_interrupt_assert(struct interrupt *interrupt); |
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void alpha_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* alpha_cpu_new(): |
* alpha_cpu_new(): |
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int alpha_cpu_new(struct cpu *cpu, struct memory *mem, |
int alpha_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
{ |
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int i; |
int i = 0; |
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struct alpha_cpu_type_def cpu_type_defs[] = ALPHA_CPU_TYPE_DEFS; |
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if (strcasecmp(cpu_type_name, "Alpha") != 0) |
/* Scan the cpu_type_defs list for this cpu type: */ |
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while (cpu_type_defs[i].name != NULL) { |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
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break; |
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} |
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i++; |
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} |
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if (cpu_type_defs[i].name == NULL) |
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return 0; |
return 0; |
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cpu->is_32bit = 0; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->memory_rw = alpha_memory_rw; |
cpu->memory_rw = alpha_memory_rw; |
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cpu->run_instr = alpha_run_instr; |
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cpu->translate_v2p = alpha_translate_v2p; |
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cpu->update_translation_table = alpha_update_translation_table; |
cpu->update_translation_table = alpha_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
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alpha_invalidate_translation_caches_paddr; |
alpha_invalidate_translation_caches; |
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cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
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cpu->is_32bit = 0; |
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cpu->cd.alpha.cpu_type = cpu_type_defs[i]; |
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/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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debug("%s", cpu->name); |
debug("%s", cpu->name); |
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} |
} |
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|
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/* Create the default virtual->physical->host translation: */ |
cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
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cpu->cd.alpha.vph_default_page = malloc(sizeof(struct alpha_vph_page)); |
|
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if (cpu->cd.alpha.vph_default_page == NULL) { |
/* Set up dummy kentry pointers to something which crashes |
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fprintf(stderr, "out of memory in alpha_cpu_new()\n"); |
the machine: */ |
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exit(1); |
store_32bit_word(cpu, 0x10010, 0x3fffffc); |
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for (i=0; i<N_ALPHA_KENTRY; i++) |
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cpu->cd.alpha.kentry[i] = 0x10010; |
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/* Bogus initial context (will be overwritten on first |
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context switch): */ |
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cpu->cd.alpha.ctx = 0x10100; |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_ALPHA_REGS; i++) |
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CPU_SETTINGS_ADD_REGISTER64(alpha_regname[i], |
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cpu->cd.alpha.r[i]); |
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/* Register the CPU interrupt pin: */ |
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{ |
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struct interrupt template; |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = cpu->path; |
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template.extra = cpu; |
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template.interrupt_assert = alpha_irq_interrupt_assert; |
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template.interrupt_deassert = alpha_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
} |
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memset(cpu->cd.alpha.vph_default_page, 0, |
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sizeof(struct alpha_vph_page)); |
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for (i=0; i<ALPHA_LEVEL0; i++) |
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cpu->cd.alpha.vph_table0[i] = cpu->cd.alpha.vph_table0_kernel[i] |
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= cpu->cd.alpha.vph_default_page; |
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cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
if (native_code_translation_enabled) |
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cpu->sampling_timer = timer_add(CPU_SAMPLE_TIMER_HZ, |
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alpha_timer_sample_tick, cpu); |
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return 1; |
return 1; |
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} |
} |
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*/ |
*/ |
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void alpha_cpu_list_available_types(void) |
void alpha_cpu_list_available_types(void) |
160 |
{ |
{ |
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/* TODO */ |
int i, j; |
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struct alpha_cpu_type_def tdefs[] = ALPHA_CPU_TYPE_DEFS; |
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debug("Alpha\n"); |
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} |
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/* |
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* alpha_cpu_register_match(): |
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*/ |
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void alpha_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
i = 0; |
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while (tdefs[i].name != NULL) { |
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if (strcasecmp(name, "pc") == 0) { |
debug("%s", tdefs[i].name); |
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if (writeflag) { |
for (j=13 - strlen(tdefs[i].name); j>0; j--) |
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m->cpus[cpunr]->pc = *valuep; |
debug(" "); |
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} else |
i++; |
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*valuep = m->cpus[cpunr]->pc; |
if ((i % 4) == 0 || tdefs[i].name == NULL) |
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*match_register = 1; |
debug("\n"); |
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} |
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/* Register names: */ |
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for (i=0; i<N_ALPHA_REGS; i++) { |
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if (strcasecmp(name, alpha_regname[i]) == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.alpha.r[i] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.alpha.r[i]; |
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*match_register = 1; |
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} |
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} |
} |
173 |
} |
} |
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if (gprs) { |
if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
cpu->pc, &offset); |
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debug("cpu%i:\t pc = 0x%016llx", x, (long long)cpu->pc); |
debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t) cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_ALPHA_REGS; i++) { |
for (i=0; i<N_ALPHA_REGS; i++) { |
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int r = (i >> 1) + ((i & 1) << 4); |
int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
if ((i % 2) == 0) |
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debug("cpu%i:\t", x); |
debug("cpu%i:\t", x); |
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if (r != ALPHA_ZERO) |
if (r != ALPHA_ZERO) |
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debug("%3s = 0x%016llx", alpha_regname[r], |
debug("%3s = 0x%016"PRIx64, alpha_regname[r], |
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(long long)cpu->cd.alpha.r[r]); |
(uint64_t) cpu->cd.alpha.r[r]); |
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debug((i % 2) == 1? "\n" : " "); |
debug((i % 2) == 1? "\n" : " "); |
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} |
} |
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} |
} |
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/* |
/* |
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* alpha_cpu_show_full_statistics(): |
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* |
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* Show detailed statistics on opcode usage on each cpu. |
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*/ |
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void alpha_cpu_show_full_statistics(struct machine *m) |
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{ |
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fatal("alpha_cpu_show_full_statistics(): TODO\n"); |
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} |
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/* |
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* alpha_cpu_tlbdump(): |
* alpha_cpu_tlbdump(): |
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* |
* |
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* Called from the debugger to dump the TLB in a readable format. |
* Called from the debugger to dump the TLB in a readable format. |
216 |
*/ |
*/ |
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void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag) |
void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag) |
218 |
{ |
{ |
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fatal("alpha_cpu_tlbdump(): TODO\n"); |
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} |
} |
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/* |
/* |
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* alpha_cpu_interrupt(): |
* alpha_irq_interrupt_assert(): |
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* alpha_irq_interrupt_deassert(): |
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*/ |
*/ |
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int alpha_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void alpha_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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fatal("alpha_cpu_interrupt(): TODO\n"); |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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return 0; |
cpu->cd.alpha.irq_asserted = 1; |
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} |
} |
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void alpha_irq_interrupt_deassert(struct interrupt *interrupt) |
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/* |
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* alpha_cpu_interrupt_ack(): |
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*/ |
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int alpha_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
{ |
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/* fatal("alpha_cpu_interrupt_ack(): TODO\n"); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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return 0; |
cpu->cd.alpha.irq_asserted = 0; |
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} |
} |
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* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
271 |
*/ |
*/ |
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int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
273 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
274 |
{ |
{ |
275 |
uint32_t iw; |
uint32_t iw; |
276 |
uint64_t offset, tmp; |
uint64_t offset, tmp; |
289 |
if (cpu->machine->ncpus > 1 && running) |
if (cpu->machine->ncpus > 1 && running) |
290 |
debug("cpu%i:\t", cpu->cpu_id); |
debug("cpu%i:\t", cpu->cpu_id); |
291 |
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292 |
debug("%016llx: ", (long long)dumpaddr); |
debug("%016"PRIx64": ", (uint64_t) dumpaddr); |
293 |
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294 |
iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
295 |
debug("%08x\t", (int)iw); |
debug("%08x\t", (int)iw); |
426 |
case 0x061: mnem = "amask"; break; |
case 0x061: mnem = "amask"; break; |
427 |
case 0x064: mnem = "cmovle"; break; |
case 0x064: mnem = "cmovle"; break; |
428 |
case 0x066: mnem = "cmovgt"; break; |
case 0x066: mnem = "cmovgt"; break; |
429 |
|
case 0x06c: mnem = "implver"; break; |
430 |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
431 |
opcode, func); |
opcode, func); |
432 |
} |
} |
445 |
else |
else |
446 |
debug("mov\t%s,%s\n", alpha_regname[ra], |
debug("mov\t%s,%s\n", alpha_regname[ra], |
447 |
alpha_regname[rc]); |
alpha_regname[rc]); |
448 |
|
} else if (func == 0x1ec) { |
449 |
|
/* implver */ |
450 |
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debug("%s\t%s\n", mnem, alpha_regname[rc]); |
451 |
} else if (func & 0x80) |
} else if (func & 0x80) |
452 |
debug("%s\t%s,0x%x,%s\n", mnem, |
debug("%s\t%s,0x%x,%s\n", mnem, |
453 |
alpha_regname[ra], (rb << 3) + (func >> 8), |
alpha_regname[ra], (rb << 3) + (func >> 8), |
519 |
break; |
break; |
520 |
case 0x16: |
case 0x16: |
521 |
switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
522 |
|
case 0x02f: mnem = "cvttq/c"; rbrc = 1; break; |
523 |
case 0x080: mnem = "adds"; break; |
case 0x080: mnem = "adds"; break; |
524 |
case 0x081: mnem = "subs"; break; |
case 0x081: mnem = "subs"; break; |
525 |
case 0x082: mnem = "muls"; break; |
case 0x082: mnem = "muls"; break; |
526 |
case 0x083: mnem = "mult"; break; |
case 0x083: mnem = "XXXx083"; break; |
527 |
case 0x0a0: mnem = "addt"; break; |
case 0x0a0: mnem = "addt"; break; |
528 |
case 0x0a1: mnem = "subt"; break; |
case 0x0a1: mnem = "subt"; break; |
529 |
case 0x0a2: mnem = "mult"; break; |
case 0x0a2: mnem = "mult"; break; |
530 |
case 0x0a3: mnem = "divt"; break; |
case 0x0a3: mnem = "divt"; break; |
531 |
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case 0x0a5: mnem = "cmpteq"; break; |
532 |
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case 0x0a6: mnem = "cmptlt"; break; |
533 |
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case 0x0a7: mnem = "cmptle"; break; |
534 |
case 0x0be: mnem = "cvtqt"; rbrc = 1; break; |
case 0x0be: mnem = "cvtqt"; rbrc = 1; break; |
535 |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
536 |
opcode, func); |
opcode, func); |
545 |
case 0x17: |
case 0x17: |
546 |
switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
547 |
case 0x020: mnem = "fabs"; rbrc = 1; break; |
case 0x020: mnem = "fabs"; rbrc = 1; break; |
548 |
|
case 0x021: mnem = "fneg"; rbrc = 1; break; |
549 |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
550 |
opcode, func); |
opcode, func); |
551 |
} |
} |
600 |
debug("jsr"); |
debug("jsr"); |
601 |
debug("\t%s,", alpha_regname[ra]); |
debug("\t%s,", alpha_regname[ra]); |
602 |
debug("(%s),", alpha_regname[rb]); |
debug("(%s),", alpha_regname[rb]); |
603 |
debug("0x%llx", (long long)tmp); |
debug("0x%"PRIx64, (uint64_t) tmp); |
604 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
605 |
tmp, &offset); |
tmp, &offset); |
606 |
if (symbol != NULL) |
if (symbol != NULL) |
622 |
debug("%s\t", opcode==0x30? "br" : "bsr"); |
debug("%s\t", opcode==0x30? "br" : "bsr"); |
623 |
if (ra != ALPHA_ZERO) |
if (ra != ALPHA_ZERO) |
624 |
debug("%s,", alpha_regname[ra]); |
debug("%s,", alpha_regname[ra]); |
625 |
debug("0x%llx", (long long)tmp); |
debug("0x%"PRIx64, (uint64_t) tmp); |
626 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
627 |
tmp, &offset); |
tmp, &offset); |
628 |
if (symbol != NULL) |
if (symbol != NULL) |
629 |
debug("\t<%s>", symbol); |
debug("\t<%s>", symbol); |
630 |
debug("\n"); |
debug("\n"); |
631 |
break; |
break; |
632 |
|
case 0x31: |
633 |
|
case 0x35: |
634 |
case 0x38: |
case 0x38: |
635 |
case 0x39: |
case 0x39: |
636 |
case 0x3a: |
case 0x3a: |
639 |
case 0x3d: |
case 0x3d: |
640 |
case 0x3e: |
case 0x3e: |
641 |
case 0x3f: |
case 0x3f: |
642 |
|
floating = 0; |
643 |
switch (opcode) { |
switch (opcode) { |
644 |
|
case 0x31: mnem = "fbeq"; floating = 1; break; |
645 |
|
case 0x35: mnem = "fbne"; floating = 1; break; |
646 |
case 0x38: mnem = "blbc"; break; |
case 0x38: mnem = "blbc"; break; |
647 |
case 0x39: mnem = "beq"; break; |
case 0x39: mnem = "beq"; break; |
648 |
case 0x3a: mnem = "blt"; break; |
case 0x3a: mnem = "blt"; break; |
657 |
tmp |= 0xffffffffffe00000ULL; |
tmp |= 0xffffffffffe00000ULL; |
658 |
tmp <<= 2; |
tmp <<= 2; |
659 |
tmp += dumpaddr + sizeof(uint32_t); |
tmp += dumpaddr + sizeof(uint32_t); |
660 |
debug("%s\t%s,", mnem, alpha_regname[ra]); |
debug("%s\t", mnem); |
661 |
debug("0x%llx", (long long)tmp); |
if (floating) |
662 |
|
debug("f%i,", ra); |
663 |
|
else |
664 |
|
debug("%s,", alpha_regname[ra]); |
665 |
|
debug("0x%"PRIx64, (uint64_t) tmp); |
666 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
667 |
tmp, &offset); |
tmp, &offset); |
668 |
if (symbol != NULL) |
if (symbol != NULL) |