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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_alpha.c,v 1.23 2006/09/19 10:50:08 debug Exp $ |
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* |
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* Alpha CPU emulation. |
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* |
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* TODO: Many things. |
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* |
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* See http://www.eecs.harvard.edu/~nr/toolkit/specs/alpha.html for info |
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* on instruction formats etc. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
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#define DYNTRANS_8K |
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#define DYNTRANS_PAGESIZE 8192 |
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#include "tmp_alpha_head.c" |
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/* Alpha symbolic register names: */ |
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static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
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/* |
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* alpha_cpu_new(): |
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* |
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* Create a new Alpha CPU object by filling the CPU struct. |
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* Return 1 on success, 0 if cpu_type_name isn't a valid Alpha processor. |
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*/ |
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int alpha_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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int i = 0; |
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struct alpha_cpu_type_def cpu_type_defs[] = ALPHA_CPU_TYPE_DEFS; |
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/* Scan the cpu_type_defs list for this cpu type: */ |
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while (cpu_type_defs[i].name != NULL) { |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
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break; |
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} |
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i++; |
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} |
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if (cpu_type_defs[i].name == NULL) |
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return 0; |
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cpu->is_32bit = 0; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->memory_rw = alpha_memory_rw; |
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cpu->run_instr = alpha_run_instr; |
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cpu->translate_v2p = alpha_translate_v2p; |
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cpu->update_translation_table = alpha_update_translation_table; |
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cpu->invalidate_translation_caches = |
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alpha_invalidate_translation_caches; |
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cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
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cpu->cd.alpha.cpu_type = cpu_type_defs[i]; |
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/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
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/* Set up dummy kentry pointers to something which crashes |
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the machine: */ |
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store_32bit_word(cpu, 0x10010, 0x3fffffc); |
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for (i=0; i<N_ALPHA_KENTRY; i++) |
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cpu->cd.alpha.kentry[i] = 0x10010; |
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/* Bogus initial context (will be overwritten on first |
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context switch): */ |
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cpu->cd.alpha.ctx = 0x10100; |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_ALPHA_REGS; i++) |
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CPU_SETTINGS_ADD_REGISTER64(alpha_regname[i], |
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cpu->cd.alpha.r[i]); |
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return 1; |
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} |
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/* |
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* alpha_cpu_dumpinfo(): |
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*/ |
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void alpha_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* TODO */ |
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debug("\n"); |
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} |
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/* |
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* alpha_cpu_list_available_types(): |
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* |
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* Print a list of available Alpha CPU types. |
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*/ |
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void alpha_cpu_list_available_types(void) |
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{ |
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int i, j; |
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struct alpha_cpu_type_def tdefs[] = ALPHA_CPU_TYPE_DEFS; |
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i = 0; |
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while (tdefs[i].name != NULL) { |
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debug("%s", tdefs[i].name); |
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for (j=13 - strlen(tdefs[i].name); j>0; j--) |
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debug(" "); |
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i++; |
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if ((i % 4) == 0 || tdefs[i].name == NULL) |
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debug("\n"); |
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} |
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} |
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/* |
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* alpha_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void alpha_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t) cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_ALPHA_REGS; i++) { |
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int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
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debug("cpu%i:\t", x); |
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if (r != ALPHA_ZERO) |
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debug("%3s = 0x%016"PRIx64, alpha_regname[r], |
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(uint64_t) cpu->cd.alpha.r[r]); |
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debug((i % 2) == 1? "\n" : " "); |
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} |
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} |
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} |
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/* |
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* alpha_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
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size_t maxlen, int len) |
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{ |
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char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
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if (len == 4) |
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value &= 0xffffffffULL; |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
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if (len == 4) { |
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value = ((value & 0xff) << 24) + |
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((value & 0xff00) << 8) + |
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((value & 0xff0000) >> 8) + |
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((value & 0xff000000) >> 24); |
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} else { |
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value = ((value & 0xff) << 56) + |
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((value & 0xff00) << 40) + |
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((value & 0xff0000) << 24) + |
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((value & 0xff000000ULL) << 8) + |
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((value & 0xff00000000ULL) >> 8) + |
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((value & 0xff0000000000ULL) >> 24) + |
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((value & 0xff000000000000ULL) >> 40) + |
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((value & 0xff00000000000000ULL) >> 56); |
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} |
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} |
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snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
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} |
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/* |
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* alpha_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *alpha_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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if (strcmp(cmd, "g") == 0) { |
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int i; |
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char *r; |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 1 + 76 * wlen; |
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r = malloc(len); |
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if (r == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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r[0] = '\0'; |
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for (i=0; i<128; i++) |
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add_response_word(cpu, r, i, len, wlen); |
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return r; |
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} |
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if (cmd[0] == 'p') { |
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int regnr = strtol(cmd + 1, NULL, 16); |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 2 * wlen + 1; |
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char *r = malloc(len); |
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r[0] = '\0'; |
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if (regnr >= 0 && regnr <= 31) { |
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add_response_word(cpu, r, |
259 |
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cpu->cd.alpha.r[regnr], len, wlen); |
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} else if (regnr >= 32 && regnr <= 62) { |
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add_response_word(cpu, r, |
262 |
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cpu->cd.alpha.f[regnr - 32], len, wlen); |
263 |
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} else if (regnr == 0x3f) { |
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add_response_word(cpu, r, cpu->cd.alpha.fpcr, |
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len, wlen); |
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} else if (regnr == 0x40) { |
267 |
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add_response_word(cpu, r, cpu->pc, len, wlen); |
268 |
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} else { |
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/* Unimplemented: */ |
270 |
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add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
271 |
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} |
272 |
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return r; |
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} |
274 |
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275 |
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fatal("alpha_cpu_gdb_stub(): TODO\n"); |
276 |
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return NULL; |
277 |
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} |
278 |
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279 |
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280 |
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/* |
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* alpha_cpu_interrupt(): |
282 |
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*/ |
283 |
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int alpha_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
284 |
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{ |
285 |
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fatal("alpha_cpu_interrupt(): TODO\n"); |
286 |
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return 0; |
287 |
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} |
288 |
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289 |
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290 |
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/* |
291 |
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* alpha_cpu_interrupt_ack(): |
292 |
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*/ |
293 |
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int alpha_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
294 |
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{ |
295 |
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/* fatal("alpha_cpu_interrupt_ack(): TODO\n"); */ |
296 |
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return 0; |
297 |
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} |
298 |
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299 |
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300 |
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/* |
301 |
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* alpha_print_imm16_disp(): |
302 |
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* |
303 |
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* Used internally by alpha_cpu_disassemble_instr(). |
304 |
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*/ |
305 |
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static void alpha_print_imm16_disp(int imm, int rb) |
306 |
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{ |
307 |
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imm = (int16_t)imm; |
308 |
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309 |
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if (imm < 0) { |
310 |
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debug("-"); |
311 |
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imm = -imm; |
312 |
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} |
313 |
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if (imm <= 256) |
314 |
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debug("%i", imm); |
315 |
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else |
316 |
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debug("0x%x", imm); |
317 |
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if (rb != ALPHA_ZERO) |
318 |
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debug("(%s)", alpha_regname[rb]); |
319 |
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} |
320 |
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321 |
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322 |
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/* |
323 |
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* alpha_cpu_disassemble_instr(): |
324 |
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* |
325 |
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* Convert an instruction word into human readable format, for instruction |
326 |
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* tracing. |
327 |
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* |
328 |
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* If running is 1, cpu->pc should be the address of the instruction. |
329 |
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* |
330 |
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* If running is 0, things that depend on the runtime environment (eg. |
331 |
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* register contents) will not be shown, and addr will be used instead of |
332 |
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* cpu->pc for relative addresses. |
333 |
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*/ |
334 |
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int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
335 |
dpavlin |
24 |
int running, uint64_t dumpaddr) |
336 |
dpavlin |
14 |
{ |
337 |
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uint32_t iw; |
338 |
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uint64_t offset, tmp; |
339 |
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int opcode, ra, rb, func, rc, imm, floating, rbrc = 0, indir = 0; |
340 |
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char *symbol, *mnem = NULL; |
341 |
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char palcode_name[30]; |
342 |
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343 |
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if (running) |
344 |
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dumpaddr = cpu->pc; |
345 |
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346 |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
347 |
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dumpaddr, &offset); |
348 |
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if (symbol != NULL && offset == 0) |
349 |
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debug("<%s>\n", symbol); |
350 |
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351 |
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if (cpu->machine->ncpus > 1 && running) |
352 |
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debug("cpu%i:\t", cpu->cpu_id); |
353 |
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354 |
dpavlin |
24 |
debug("%016"PRIx64": ", (uint64_t) dumpaddr); |
355 |
dpavlin |
14 |
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356 |
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iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
357 |
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debug("%08x\t", (int)iw); |
358 |
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359 |
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opcode = iw >> 26; |
360 |
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ra = (iw >> 21) & 31; |
361 |
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rb = (iw >> 16) & 31; |
362 |
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func = (iw >> 5) & 0x7ff; |
363 |
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rc = iw & 31; |
364 |
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imm = iw & 0xffff; |
365 |
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366 |
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switch (opcode) { |
367 |
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case 0x00: |
368 |
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alpha_palcode_name(iw & 0x3ffffff, palcode_name, |
369 |
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sizeof(palcode_name)); |
370 |
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debug("call_pal %s\n", palcode_name); |
371 |
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break; |
372 |
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case 0x08: |
373 |
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case 0x09: |
374 |
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debug("lda%s\t%s,", opcode == 9? "h" : "", alpha_regname[ra]); |
375 |
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alpha_print_imm16_disp(imm, rb); |
376 |
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debug("\n"); |
377 |
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break; |
378 |
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case 0x0a: |
379 |
|
|
case 0x0b: |
380 |
|
|
case 0x0c: |
381 |
|
|
case 0x0d: |
382 |
|
|
case 0x0e: |
383 |
|
|
case 0x0f: |
384 |
|
|
case 0x20: |
385 |
|
|
case 0x21: |
386 |
|
|
case 0x22: |
387 |
|
|
case 0x23: |
388 |
|
|
case 0x24: |
389 |
|
|
case 0x25: |
390 |
|
|
case 0x26: |
391 |
|
|
case 0x27: |
392 |
|
|
case 0x28: |
393 |
|
|
case 0x29: |
394 |
|
|
case 0x2a: |
395 |
|
|
case 0x2b: |
396 |
|
|
case 0x2c: |
397 |
|
|
case 0x2d: |
398 |
|
|
case 0x2e: |
399 |
|
|
case 0x2f: |
400 |
|
|
floating = 0; |
401 |
|
|
switch (opcode) { |
402 |
|
|
case 0x0a: mnem = "ldbu"; break; |
403 |
|
|
case 0x0b: mnem = "ldq_u"; break; |
404 |
|
|
case 0x0c: mnem = "ldwu"; break; |
405 |
|
|
case 0x0d: mnem = "stw"; break; |
406 |
|
|
case 0x0e: mnem = "stb"; break; |
407 |
|
|
case 0x0f: mnem = "stq_u"; break; |
408 |
|
|
case 0x20: mnem = "ldf"; floating = 1; break; |
409 |
|
|
case 0x21: mnem = "ldg"; floating = 1; break; |
410 |
|
|
case 0x22: mnem = "lds"; floating = 1; break; |
411 |
|
|
case 0x23: mnem = "ldt"; floating = 1; break; |
412 |
|
|
case 0x24: mnem = "stf"; floating = 1; break; |
413 |
|
|
case 0x25: mnem = "stg"; floating = 1; break; |
414 |
|
|
case 0x26: mnem = "sts"; floating = 1; break; |
415 |
|
|
case 0x27: mnem = "stt"; floating = 1; break; |
416 |
|
|
case 0x28: mnem = "ldl"; break; |
417 |
|
|
case 0x29: mnem = "ldq"; break; |
418 |
|
|
case 0x2a: mnem = "ldl_l"; break; |
419 |
|
|
case 0x2b: mnem = "ldq_l"; break; |
420 |
|
|
case 0x2c: mnem = "stl"; break; |
421 |
|
|
case 0x2d: mnem = "stq"; break; |
422 |
|
|
case 0x2e: mnem = "stl_c"; break; |
423 |
|
|
case 0x2f: mnem = "stq_c"; break; |
424 |
|
|
} |
425 |
|
|
if (opcode == 0x0b && ra == ALPHA_ZERO) { |
426 |
|
|
debug("unop"); |
427 |
|
|
} else { |
428 |
|
|
debug("%s\t", mnem); |
429 |
|
|
if (floating) |
430 |
|
|
debug("f%i,", ra); |
431 |
|
|
else |
432 |
|
|
debug("%s,", alpha_regname[ra]); |
433 |
|
|
alpha_print_imm16_disp(imm, rb); |
434 |
|
|
} |
435 |
|
|
debug("\n"); |
436 |
|
|
break; |
437 |
|
|
case 0x10: |
438 |
|
|
switch (func & 0x7f) { |
439 |
|
|
case 0x00: mnem = "addl"; break; |
440 |
|
|
case 0x02: mnem = "s4addl"; break; |
441 |
|
|
case 0x09: mnem = "subl"; break; |
442 |
|
|
case 0x0b: mnem = "s4subl"; break; |
443 |
|
|
case 0x0f: mnem = "cmpbge"; break; |
444 |
|
|
case 0x12: mnem = "s8addl"; break; |
445 |
|
|
case 0x1b: mnem = "s8subl"; break; |
446 |
|
|
case 0x1d: mnem = "cmpult"; break; |
447 |
|
|
case 0x20: mnem = "addq"; break; |
448 |
|
|
case 0x22: mnem = "s4addq"; break; |
449 |
|
|
case 0x29: mnem = "subq"; break; |
450 |
|
|
case 0x2b: mnem = "s4subq"; break; |
451 |
|
|
case 0x2d: mnem = "cmpeq"; break; |
452 |
|
|
case 0x32: mnem = "s8addq"; break; |
453 |
|
|
case 0x3b: mnem = "s8subq"; break; |
454 |
|
|
case 0x3d: mnem = "cmpule"; break; |
455 |
|
|
case 0x40: mnem = "addl/v"; break; |
456 |
|
|
case 0x49: mnem = "subl/v"; break; |
457 |
|
|
case 0x4d: mnem = "cmplt"; break; |
458 |
|
|
case 0x60: mnem = "addq/v"; break; |
459 |
|
|
case 0x69: mnem = "subq/v"; break; |
460 |
|
|
case 0x6d: mnem = "cmple"; break; |
461 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
462 |
|
|
opcode, func); |
463 |
|
|
} |
464 |
|
|
if (mnem == NULL) |
465 |
|
|
break; |
466 |
|
|
if (func & 0x80) |
467 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
468 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
469 |
|
|
alpha_regname[rc]); |
470 |
|
|
else |
471 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
472 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
473 |
|
|
break; |
474 |
|
|
case 0x11: |
475 |
|
|
switch (func & 0x7f) { |
476 |
|
|
case 0x000: mnem = "and"; break; |
477 |
|
|
case 0x008: mnem = "andnot"; break; |
478 |
|
|
case 0x014: mnem = "cmovlbs"; break; |
479 |
|
|
case 0x016: mnem = "cmovlbc"; break; |
480 |
|
|
case 0x020: mnem = "or"; break; |
481 |
|
|
case 0x024: mnem = "cmoveq"; break; |
482 |
|
|
case 0x026: mnem = "cmovne"; break; |
483 |
|
|
case 0x028: mnem = "ornot"; break; |
484 |
|
|
case 0x040: mnem = "xor"; break; |
485 |
|
|
case 0x044: mnem = "cmovlt"; break; |
486 |
|
|
case 0x046: mnem = "cmovge"; break; |
487 |
|
|
case 0x048: mnem = "eqv"; break; |
488 |
|
|
case 0x061: mnem = "amask"; break; |
489 |
|
|
case 0x064: mnem = "cmovle"; break; |
490 |
|
|
case 0x066: mnem = "cmovgt"; break; |
491 |
dpavlin |
32 |
case 0x06c: mnem = "implver"; break; |
492 |
dpavlin |
14 |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
493 |
|
|
opcode, func); |
494 |
|
|
} |
495 |
|
|
if (mnem == NULL) |
496 |
|
|
break; |
497 |
|
|
/* Special cases: "nop" etc: */ |
498 |
|
|
if (func == 0x020 && rc == ALPHA_ZERO) |
499 |
|
|
debug("nop\n"); |
500 |
|
|
else if (func == 0x020 && (ra == ALPHA_ZERO |
501 |
|
|
|| rb == ALPHA_ZERO)) { |
502 |
|
|
if (ra == ALPHA_ZERO && rb == ALPHA_ZERO) |
503 |
|
|
debug("clr\t%s\n", alpha_regname[rc]); |
504 |
|
|
else if (ra == ALPHA_ZERO) |
505 |
|
|
debug("mov\t%s,%s\n", alpha_regname[rb], |
506 |
|
|
alpha_regname[rc]); |
507 |
|
|
else |
508 |
|
|
debug("mov\t%s,%s\n", alpha_regname[ra], |
509 |
|
|
alpha_regname[rc]); |
510 |
dpavlin |
32 |
} else if (func == 0x1ec) { |
511 |
|
|
/* implver */ |
512 |
|
|
debug("%s\t%s\n", mnem, alpha_regname[rc]); |
513 |
dpavlin |
14 |
} else if (func & 0x80) |
514 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
515 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
516 |
|
|
alpha_regname[rc]); |
517 |
|
|
else |
518 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
519 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
520 |
|
|
break; |
521 |
|
|
case 0x12: |
522 |
|
|
switch (func & 0x7f) { |
523 |
|
|
case 0x02: mnem = "mskbl"; break; |
524 |
|
|
case 0x06: mnem = "extbl"; break; |
525 |
|
|
case 0x0b: mnem = "insbl"; break; |
526 |
|
|
case 0x12: mnem = "mskwl"; break; |
527 |
|
|
case 0x16: mnem = "extwl"; break; |
528 |
|
|
case 0x1b: mnem = "inswl"; break; |
529 |
|
|
case 0x22: mnem = "mskll"; break; |
530 |
|
|
case 0x26: mnem = "extll"; break; |
531 |
|
|
case 0x2b: mnem = "insll"; break; |
532 |
|
|
case 0x30: mnem = "zap"; break; |
533 |
|
|
case 0x31: mnem = "zapnot"; break; |
534 |
|
|
case 0x32: mnem = "mskql"; break; |
535 |
|
|
case 0x34: mnem = "srl"; break; |
536 |
|
|
case 0x36: mnem = "extql"; break; |
537 |
|
|
case 0x39: mnem = "sll"; break; |
538 |
|
|
case 0x3b: mnem = "insql"; break; |
539 |
|
|
case 0x3c: mnem = "sra"; break; |
540 |
|
|
case 0x52: mnem = "mskwh"; break; |
541 |
|
|
case 0x57: mnem = "inswh"; break; |
542 |
|
|
case 0x5a: mnem = "extwh"; break; |
543 |
|
|
case 0x62: mnem = "msklh"; break; |
544 |
|
|
case 0x67: mnem = "inslh"; break; |
545 |
|
|
case 0x6a: mnem = "extlh"; break; |
546 |
|
|
case 0x72: mnem = "mskqh"; break; |
547 |
|
|
case 0x77: mnem = "insqh"; break; |
548 |
|
|
case 0x7a: mnem = "extqh"; break; |
549 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
550 |
|
|
opcode, func); |
551 |
|
|
} |
552 |
|
|
if (mnem == NULL) |
553 |
|
|
break; |
554 |
|
|
if (func & 0x80) |
555 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
556 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
557 |
|
|
alpha_regname[rc]); |
558 |
|
|
else |
559 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
560 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
561 |
|
|
break; |
562 |
|
|
case 0x13: |
563 |
|
|
switch (func & 0x7f) { |
564 |
|
|
case 0x00: mnem = "mull"; break; |
565 |
|
|
case 0x20: mnem = "mulq"; break; |
566 |
|
|
case 0x30: mnem = "umulh"; break; |
567 |
|
|
case 0x40: mnem = "mull/v"; break; |
568 |
|
|
case 0x60: mnem = "mulq/v"; break; |
569 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
570 |
|
|
opcode, func); |
571 |
|
|
} |
572 |
|
|
if (mnem == NULL) |
573 |
|
|
break; |
574 |
|
|
if (func & 0x80) |
575 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
576 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
577 |
|
|
alpha_regname[rc]); |
578 |
|
|
else |
579 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
580 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
581 |
|
|
break; |
582 |
|
|
case 0x16: |
583 |
|
|
switch (func & 0x7ff) { |
584 |
dpavlin |
22 |
case 0x02f: mnem = "cvttq/c"; rbrc = 1; break; |
585 |
dpavlin |
14 |
case 0x080: mnem = "adds"; break; |
586 |
|
|
case 0x081: mnem = "subs"; break; |
587 |
|
|
case 0x082: mnem = "muls"; break; |
588 |
dpavlin |
22 |
case 0x083: mnem = "XXXx083"; break; |
589 |
dpavlin |
14 |
case 0x0a0: mnem = "addt"; break; |
590 |
|
|
case 0x0a1: mnem = "subt"; break; |
591 |
|
|
case 0x0a2: mnem = "mult"; break; |
592 |
|
|
case 0x0a3: mnem = "divt"; break; |
593 |
dpavlin |
22 |
case 0x0a5: mnem = "cmpteq"; break; |
594 |
|
|
case 0x0a6: mnem = "cmptlt"; break; |
595 |
|
|
case 0x0a7: mnem = "cmptle"; break; |
596 |
dpavlin |
14 |
case 0x0be: mnem = "cvtqt"; rbrc = 1; break; |
597 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
598 |
|
|
opcode, func); |
599 |
|
|
} |
600 |
|
|
if (mnem == NULL) |
601 |
|
|
break; |
602 |
|
|
if (rbrc) |
603 |
|
|
debug("%s\tf%i,f%i\n", mnem, rb, rc); |
604 |
|
|
else |
605 |
|
|
debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc); |
606 |
|
|
break; |
607 |
|
|
case 0x17: |
608 |
|
|
switch (func & 0x7ff) { |
609 |
|
|
case 0x020: mnem = "fabs"; rbrc = 1; break; |
610 |
dpavlin |
22 |
case 0x021: mnem = "fneg"; rbrc = 1; break; |
611 |
dpavlin |
14 |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
612 |
|
|
opcode, func); |
613 |
|
|
} |
614 |
|
|
if (mnem == NULL) |
615 |
|
|
break; |
616 |
|
|
if ((func & 0x7ff) == 0x020 && ra == 31 && rb == 31) |
617 |
|
|
debug("fclr\tf%i\n", rc); |
618 |
|
|
else if (rbrc) |
619 |
|
|
debug("%s\tf%i,f%i\n", mnem, rb, rc); |
620 |
|
|
else |
621 |
|
|
debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc); |
622 |
|
|
break; |
623 |
|
|
case 0x18: |
624 |
|
|
switch (iw & 0xffff) { |
625 |
|
|
case 0x0000: mnem = "trapb"; break; |
626 |
|
|
case 0x0400: mnem = "excb"; break; |
627 |
|
|
case 0x4000: mnem = "mb"; break; |
628 |
|
|
case 0x4400: mnem = "wmb"; break; |
629 |
|
|
case 0x8000: mnem = "fetch"; indir = 1; break; |
630 |
|
|
case 0xa000: mnem = "fetch_m"; indir = 1; break; |
631 |
|
|
case 0xc000: mnem = "rpcc"; break; |
632 |
|
|
case 0xe000: mnem = "rc"; break; |
633 |
|
|
case 0xe800: mnem = "ecb"; indir = 1; break; |
634 |
|
|
case 0xf000: mnem = "rs"; break; |
635 |
|
|
case 0xf800: mnem = "wh64"; indir = 1; break; |
636 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
637 |
|
|
opcode, func); |
638 |
|
|
} |
639 |
|
|
if (mnem == NULL) |
640 |
|
|
break; |
641 |
|
|
debug("%s", mnem); |
642 |
|
|
if ((iw & 0xffff) >= 0x8000) { |
643 |
|
|
debug("\t"); |
644 |
|
|
if (indir) |
645 |
|
|
debug("(%s)", alpha_regname[rb]); |
646 |
|
|
else |
647 |
|
|
debug("%s", alpha_regname[ra]); |
648 |
|
|
} |
649 |
|
|
debug("\n"); |
650 |
|
|
break; |
651 |
|
|
case 0x1a: |
652 |
|
|
tmp = iw & 0x3fff; |
653 |
|
|
if (tmp & 0x2000) |
654 |
|
|
tmp |= 0xffffffffffffc000ULL; |
655 |
|
|
tmp <<= 2; |
656 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
657 |
|
|
switch ((iw >> 14) & 3) { |
658 |
|
|
case 0: |
659 |
|
|
case 1: if (((iw >> 14) & 3) == 0) |
660 |
|
|
debug("jmp"); |
661 |
|
|
else |
662 |
|
|
debug("jsr"); |
663 |
|
|
debug("\t%s,", alpha_regname[ra]); |
664 |
|
|
debug("(%s),", alpha_regname[rb]); |
665 |
dpavlin |
24 |
debug("0x%"PRIx64, (uint64_t) tmp); |
666 |
dpavlin |
14 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
667 |
|
|
tmp, &offset); |
668 |
|
|
if (symbol != NULL) |
669 |
|
|
debug("\t<%s>", symbol); |
670 |
|
|
break; |
671 |
|
|
case 2: debug("ret"); |
672 |
|
|
break; |
673 |
|
|
default:fatal("unimpl JSR!"); |
674 |
|
|
} |
675 |
|
|
debug("\n"); |
676 |
|
|
break; |
677 |
|
|
case 0x30: |
678 |
|
|
case 0x34: |
679 |
|
|
tmp = iw & 0x1fffff; |
680 |
|
|
if (tmp & 0x100000) |
681 |
|
|
tmp |= 0xffffffffffe00000ULL; |
682 |
|
|
tmp <<= 2; |
683 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
684 |
|
|
debug("%s\t", opcode==0x30? "br" : "bsr"); |
685 |
|
|
if (ra != ALPHA_ZERO) |
686 |
|
|
debug("%s,", alpha_regname[ra]); |
687 |
dpavlin |
24 |
debug("0x%"PRIx64, (uint64_t) tmp); |
688 |
dpavlin |
14 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
689 |
|
|
tmp, &offset); |
690 |
|
|
if (symbol != NULL) |
691 |
|
|
debug("\t<%s>", symbol); |
692 |
|
|
debug("\n"); |
693 |
|
|
break; |
694 |
dpavlin |
22 |
case 0x31: |
695 |
|
|
case 0x35: |
696 |
dpavlin |
14 |
case 0x38: |
697 |
|
|
case 0x39: |
698 |
|
|
case 0x3a: |
699 |
|
|
case 0x3b: |
700 |
|
|
case 0x3c: |
701 |
|
|
case 0x3d: |
702 |
|
|
case 0x3e: |
703 |
|
|
case 0x3f: |
704 |
dpavlin |
22 |
floating = 0; |
705 |
dpavlin |
14 |
switch (opcode) { |
706 |
dpavlin |
22 |
case 0x31: mnem = "fbeq"; floating = 1; break; |
707 |
|
|
case 0x35: mnem = "fbne"; floating = 1; break; |
708 |
dpavlin |
14 |
case 0x38: mnem = "blbc"; break; |
709 |
|
|
case 0x39: mnem = "beq"; break; |
710 |
|
|
case 0x3a: mnem = "blt"; break; |
711 |
|
|
case 0x3b: mnem = "ble"; break; |
712 |
|
|
case 0x3c: mnem = "blbs"; break; |
713 |
|
|
case 0x3d: mnem = "bne"; break; |
714 |
|
|
case 0x3e: mnem = "bge"; break; |
715 |
|
|
case 0x3f: mnem = "bgt"; break; |
716 |
|
|
} |
717 |
|
|
tmp = iw & 0x1fffff; |
718 |
|
|
if (tmp & 0x100000) |
719 |
|
|
tmp |= 0xffffffffffe00000ULL; |
720 |
|
|
tmp <<= 2; |
721 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
722 |
dpavlin |
22 |
debug("%s\t", mnem); |
723 |
|
|
if (floating) |
724 |
|
|
debug("f%i,", ra); |
725 |
|
|
else |
726 |
|
|
debug("%s,", alpha_regname[ra]); |
727 |
dpavlin |
24 |
debug("0x%"PRIx64, (uint64_t) tmp); |
728 |
dpavlin |
14 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
729 |
|
|
tmp, &offset); |
730 |
|
|
if (symbol != NULL) |
731 |
|
|
debug("\t<%s>", symbol); |
732 |
|
|
debug("\n"); |
733 |
|
|
break; |
734 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x\n", opcode); |
735 |
|
|
} |
736 |
|
|
|
737 |
|
|
return sizeof(uint32_t); |
738 |
|
|
} |
739 |
|
|
|
740 |
|
|
|
741 |
|
|
#define MEMORY_RW alpha_userland_memory_rw |
742 |
|
|
#define MEM_ALPHA |
743 |
|
|
#define MEM_USERLAND |
744 |
|
|
#include "../memory_rw.c" |
745 |
|
|
#undef MEM_USERLAND |
746 |
|
|
#undef MEM_ALPHA |
747 |
|
|
#undef MEMORY_RW |
748 |
|
|
|
749 |
|
|
|
750 |
|
|
#include "tmp_alpha_tail.c" |
751 |
|
|
|