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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
18 |
* $Id: cpu_alpha.c,v 1.2 2005/10/22 17:24:20 debug Exp $ |
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dpavlin |
14 |
* |
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* Alpha CPU emulation. |
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* |
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* TODO: Many things. |
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* |
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* See http://www.eecs.harvard.edu/~nr/toolkit/specs/alpha.html for info |
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* on instruction formats etc. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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#define DYNTRANS_8K |
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#define DYNTRANS_PAGESIZE 8192 |
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#include "tmp_alpha_head.c" |
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/* Alpha symbolic register names: */ |
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static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
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/* |
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* alpha_cpu_new(): |
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* |
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* Create a new Alpha CPU object by filling the CPU struct. |
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* Return 1 on success, 0 if cpu_type_name isn't a valid Alpha processor. |
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*/ |
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int alpha_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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int i; |
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if (strcasecmp(cpu_type_name, "Alpha") != 0) |
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return 0; |
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cpu->memory_rw = alpha_memory_rw; |
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cpu->update_translation_table = alpha_update_translation_table; |
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dpavlin |
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cpu->invalidate_translation_caches = |
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alpha_invalidate_translation_caches; |
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dpavlin |
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cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
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cpu->is_32bit = 0; |
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/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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/* Create the default virtual->physical->host translation: */ |
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cpu->cd.alpha.vph_default_page = malloc(sizeof(struct alpha_vph_page)); |
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if (cpu->cd.alpha.vph_default_page == NULL) { |
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fprintf(stderr, "out of memory in alpha_cpu_new()\n"); |
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exit(1); |
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} |
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memset(cpu->cd.alpha.vph_default_page, 0, |
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sizeof(struct alpha_vph_page)); |
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for (i=0; i<ALPHA_LEVEL0; i++) |
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cpu->cd.alpha.vph_table0[i] = cpu->cd.alpha.vph_table0_kernel[i] |
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= cpu->cd.alpha.vph_default_page; |
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cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
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return 1; |
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} |
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/* |
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* alpha_cpu_dumpinfo(): |
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*/ |
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void alpha_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* TODO */ |
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debug("\n"); |
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} |
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/* |
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* alpha_cpu_list_available_types(): |
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* |
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* Print a list of available Alpha CPU types. |
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*/ |
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void alpha_cpu_list_available_types(void) |
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{ |
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/* TODO */ |
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debug("Alpha\n"); |
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} |
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/* |
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* alpha_cpu_register_match(): |
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*/ |
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void alpha_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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/* Register names: */ |
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for (i=0; i<N_ALPHA_REGS; i++) { |
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if (strcasecmp(name, alpha_regname[i]) == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.alpha.r[i] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.alpha.r[i]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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* alpha_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void alpha_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i:\t pc = 0x%016llx", x, (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_ALPHA_REGS; i++) { |
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int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
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debug("cpu%i:\t", x); |
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if (r != ALPHA_ZERO) |
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debug("%3s = 0x%016llx", alpha_regname[r], |
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(long long)cpu->cd.alpha.r[r]); |
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debug((i % 2) == 1? "\n" : " "); |
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} |
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} |
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} |
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/* |
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* alpha_cpu_show_full_statistics(): |
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* |
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* Show detailed statistics on opcode usage on each cpu. |
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*/ |
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void alpha_cpu_show_full_statistics(struct machine *m) |
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{ |
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fatal("alpha_cpu_show_full_statistics(): TODO\n"); |
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} |
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/* |
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* alpha_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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fatal("alpha_cpu_tlbdump(): TODO\n"); |
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} |
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/* |
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* alpha_cpu_interrupt(): |
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*/ |
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int alpha_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("alpha_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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/* |
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* alpha_cpu_interrupt_ack(): |
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*/ |
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int alpha_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("alpha_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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/* |
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* alpha_print_imm16_disp(): |
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* |
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* Used internally by alpha_cpu_disassemble_instr(). |
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*/ |
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static void alpha_print_imm16_disp(int imm, int rb) |
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{ |
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imm = (int16_t)imm; |
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if (imm < 0) { |
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debug("-"); |
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imm = -imm; |
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} |
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if (imm <= 256) |
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debug("%i", imm); |
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else |
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debug("0x%x", imm); |
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if (rb != ALPHA_ZERO) |
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debug("(%s)", alpha_regname[rb]); |
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} |
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/* |
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* alpha_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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uint32_t iw; |
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uint64_t offset, tmp; |
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int opcode, ra, rb, func, rc, imm, floating, rbrc = 0, indir = 0; |
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char *symbol, *mnem = NULL; |
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char palcode_name[30]; |
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if (running) |
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dumpaddr = cpu->pc; |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset == 0) |
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debug("<%s>\n", symbol); |
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i:\t", cpu->cpu_id); |
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debug("%016llx: ", (long long)dumpaddr); |
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iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
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debug("%08x\t", (int)iw); |
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opcode = iw >> 26; |
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ra = (iw >> 21) & 31; |
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rb = (iw >> 16) & 31; |
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func = (iw >> 5) & 0x7ff; |
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rc = iw & 31; |
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imm = iw & 0xffff; |
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switch (opcode) { |
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case 0x00: |
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alpha_palcode_name(iw & 0x3ffffff, palcode_name, |
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sizeof(palcode_name)); |
| 306 |
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debug("call_pal %s\n", palcode_name); |
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break; |
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case 0x08: |
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case 0x09: |
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debug("lda%s\t%s,", opcode == 9? "h" : "", alpha_regname[ra]); |
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alpha_print_imm16_disp(imm, rb); |
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debug("\n"); |
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break; |
| 314 |
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case 0x0a: |
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case 0x0b: |
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case 0x0c: |
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case 0x0d: |
| 318 |
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case 0x0e: |
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case 0x0f: |
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case 0x20: |
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case 0x21: |
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case 0x22: |
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case 0x23: |
| 324 |
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case 0x24: |
| 325 |
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case 0x25: |
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case 0x26: |
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case 0x27: |
| 328 |
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case 0x28: |
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case 0x29: |
| 330 |
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case 0x2a: |
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case 0x2b: |
| 332 |
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case 0x2c: |
| 333 |
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case 0x2d: |
| 334 |
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case 0x2e: |
| 335 |
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case 0x2f: |
| 336 |
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floating = 0; |
| 337 |
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switch (opcode) { |
| 338 |
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case 0x0a: mnem = "ldbu"; break; |
| 339 |
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case 0x0b: mnem = "ldq_u"; break; |
| 340 |
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case 0x0c: mnem = "ldwu"; break; |
| 341 |
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case 0x0d: mnem = "stw"; break; |
| 342 |
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case 0x0e: mnem = "stb"; break; |
| 343 |
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case 0x0f: mnem = "stq_u"; break; |
| 344 |
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case 0x20: mnem = "ldf"; floating = 1; break; |
| 345 |
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case 0x21: mnem = "ldg"; floating = 1; break; |
| 346 |
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case 0x22: mnem = "lds"; floating = 1; break; |
| 347 |
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case 0x23: mnem = "ldt"; floating = 1; break; |
| 348 |
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case 0x24: mnem = "stf"; floating = 1; break; |
| 349 |
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case 0x25: mnem = "stg"; floating = 1; break; |
| 350 |
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case 0x26: mnem = "sts"; floating = 1; break; |
| 351 |
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case 0x27: mnem = "stt"; floating = 1; break; |
| 352 |
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case 0x28: mnem = "ldl"; break; |
| 353 |
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case 0x29: mnem = "ldq"; break; |
| 354 |
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case 0x2a: mnem = "ldl_l"; break; |
| 355 |
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case 0x2b: mnem = "ldq_l"; break; |
| 356 |
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case 0x2c: mnem = "stl"; break; |
| 357 |
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case 0x2d: mnem = "stq"; break; |
| 358 |
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case 0x2e: mnem = "stl_c"; break; |
| 359 |
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case 0x2f: mnem = "stq_c"; break; |
| 360 |
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} |
| 361 |
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if (opcode == 0x0b && ra == ALPHA_ZERO) { |
| 362 |
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debug("unop"); |
| 363 |
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} else { |
| 364 |
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debug("%s\t", mnem); |
| 365 |
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if (floating) |
| 366 |
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debug("f%i,", ra); |
| 367 |
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else |
| 368 |
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debug("%s,", alpha_regname[ra]); |
| 369 |
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alpha_print_imm16_disp(imm, rb); |
| 370 |
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} |
| 371 |
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|
debug("\n"); |
| 372 |
|
|
break; |
| 373 |
|
|
case 0x10: |
| 374 |
|
|
switch (func & 0x7f) { |
| 375 |
|
|
case 0x00: mnem = "addl"; break; |
| 376 |
|
|
case 0x02: mnem = "s4addl"; break; |
| 377 |
|
|
case 0x09: mnem = "subl"; break; |
| 378 |
|
|
case 0x0b: mnem = "s4subl"; break; |
| 379 |
|
|
case 0x0f: mnem = "cmpbge"; break; |
| 380 |
|
|
case 0x12: mnem = "s8addl"; break; |
| 381 |
|
|
case 0x1b: mnem = "s8subl"; break; |
| 382 |
|
|
case 0x1d: mnem = "cmpult"; break; |
| 383 |
|
|
case 0x20: mnem = "addq"; break; |
| 384 |
|
|
case 0x22: mnem = "s4addq"; break; |
| 385 |
|
|
case 0x29: mnem = "subq"; break; |
| 386 |
|
|
case 0x2b: mnem = "s4subq"; break; |
| 387 |
|
|
case 0x2d: mnem = "cmpeq"; break; |
| 388 |
|
|
case 0x32: mnem = "s8addq"; break; |
| 389 |
|
|
case 0x3b: mnem = "s8subq"; break; |
| 390 |
|
|
case 0x3d: mnem = "cmpule"; break; |
| 391 |
|
|
case 0x40: mnem = "addl/v"; break; |
| 392 |
|
|
case 0x49: mnem = "subl/v"; break; |
| 393 |
|
|
case 0x4d: mnem = "cmplt"; break; |
| 394 |
|
|
case 0x60: mnem = "addq/v"; break; |
| 395 |
|
|
case 0x69: mnem = "subq/v"; break; |
| 396 |
|
|
case 0x6d: mnem = "cmple"; break; |
| 397 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 398 |
|
|
opcode, func); |
| 399 |
|
|
} |
| 400 |
|
|
if (mnem == NULL) |
| 401 |
|
|
break; |
| 402 |
|
|
if (func & 0x80) |
| 403 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
| 404 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
| 405 |
|
|
alpha_regname[rc]); |
| 406 |
|
|
else |
| 407 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
| 408 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
| 409 |
|
|
break; |
| 410 |
|
|
case 0x11: |
| 411 |
|
|
switch (func & 0x7f) { |
| 412 |
|
|
case 0x000: mnem = "and"; break; |
| 413 |
|
|
case 0x008: mnem = "andnot"; break; |
| 414 |
|
|
case 0x014: mnem = "cmovlbs"; break; |
| 415 |
|
|
case 0x016: mnem = "cmovlbc"; break; |
| 416 |
|
|
case 0x020: mnem = "or"; break; |
| 417 |
|
|
case 0x024: mnem = "cmoveq"; break; |
| 418 |
|
|
case 0x026: mnem = "cmovne"; break; |
| 419 |
|
|
case 0x028: mnem = "ornot"; break; |
| 420 |
|
|
case 0x040: mnem = "xor"; break; |
| 421 |
|
|
case 0x044: mnem = "cmovlt"; break; |
| 422 |
|
|
case 0x046: mnem = "cmovge"; break; |
| 423 |
|
|
case 0x048: mnem = "eqv"; break; |
| 424 |
|
|
case 0x061: mnem = "amask"; break; |
| 425 |
|
|
case 0x064: mnem = "cmovle"; break; |
| 426 |
|
|
case 0x066: mnem = "cmovgt"; break; |
| 427 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 428 |
|
|
opcode, func); |
| 429 |
|
|
} |
| 430 |
|
|
if (mnem == NULL) |
| 431 |
|
|
break; |
| 432 |
|
|
/* Special cases: "nop" etc: */ |
| 433 |
|
|
if (func == 0x020 && rc == ALPHA_ZERO) |
| 434 |
|
|
debug("nop\n"); |
| 435 |
|
|
else if (func == 0x020 && (ra == ALPHA_ZERO |
| 436 |
|
|
|| rb == ALPHA_ZERO)) { |
| 437 |
|
|
if (ra == ALPHA_ZERO && rb == ALPHA_ZERO) |
| 438 |
|
|
debug("clr\t%s\n", alpha_regname[rc]); |
| 439 |
|
|
else if (ra == ALPHA_ZERO) |
| 440 |
|
|
debug("mov\t%s,%s\n", alpha_regname[rb], |
| 441 |
|
|
alpha_regname[rc]); |
| 442 |
|
|
else |
| 443 |
|
|
debug("mov\t%s,%s\n", alpha_regname[ra], |
| 444 |
|
|
alpha_regname[rc]); |
| 445 |
|
|
} else if (func & 0x80) |
| 446 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
| 447 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
| 448 |
|
|
alpha_regname[rc]); |
| 449 |
|
|
else |
| 450 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
| 451 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
| 452 |
|
|
break; |
| 453 |
|
|
case 0x12: |
| 454 |
|
|
switch (func & 0x7f) { |
| 455 |
|
|
case 0x02: mnem = "mskbl"; break; |
| 456 |
|
|
case 0x06: mnem = "extbl"; break; |
| 457 |
|
|
case 0x0b: mnem = "insbl"; break; |
| 458 |
|
|
case 0x12: mnem = "mskwl"; break; |
| 459 |
|
|
case 0x16: mnem = "extwl"; break; |
| 460 |
|
|
case 0x1b: mnem = "inswl"; break; |
| 461 |
|
|
case 0x22: mnem = "mskll"; break; |
| 462 |
|
|
case 0x26: mnem = "extll"; break; |
| 463 |
|
|
case 0x2b: mnem = "insll"; break; |
| 464 |
|
|
case 0x30: mnem = "zap"; break; |
| 465 |
|
|
case 0x31: mnem = "zapnot"; break; |
| 466 |
|
|
case 0x32: mnem = "mskql"; break; |
| 467 |
|
|
case 0x34: mnem = "srl"; break; |
| 468 |
|
|
case 0x36: mnem = "extql"; break; |
| 469 |
|
|
case 0x39: mnem = "sll"; break; |
| 470 |
|
|
case 0x3b: mnem = "insql"; break; |
| 471 |
|
|
case 0x3c: mnem = "sra"; break; |
| 472 |
|
|
case 0x52: mnem = "mskwh"; break; |
| 473 |
|
|
case 0x57: mnem = "inswh"; break; |
| 474 |
|
|
case 0x5a: mnem = "extwh"; break; |
| 475 |
|
|
case 0x62: mnem = "msklh"; break; |
| 476 |
|
|
case 0x67: mnem = "inslh"; break; |
| 477 |
|
|
case 0x6a: mnem = "extlh"; break; |
| 478 |
|
|
case 0x72: mnem = "mskqh"; break; |
| 479 |
|
|
case 0x77: mnem = "insqh"; break; |
| 480 |
|
|
case 0x7a: mnem = "extqh"; break; |
| 481 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 482 |
|
|
opcode, func); |
| 483 |
|
|
} |
| 484 |
|
|
if (mnem == NULL) |
| 485 |
|
|
break; |
| 486 |
|
|
if (func & 0x80) |
| 487 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
| 488 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
| 489 |
|
|
alpha_regname[rc]); |
| 490 |
|
|
else |
| 491 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
| 492 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
| 493 |
|
|
break; |
| 494 |
|
|
case 0x13: |
| 495 |
|
|
switch (func & 0x7f) { |
| 496 |
|
|
case 0x00: mnem = "mull"; break; |
| 497 |
|
|
case 0x20: mnem = "mulq"; break; |
| 498 |
|
|
case 0x30: mnem = "umulh"; break; |
| 499 |
|
|
case 0x40: mnem = "mull/v"; break; |
| 500 |
|
|
case 0x60: mnem = "mulq/v"; break; |
| 501 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 502 |
|
|
opcode, func); |
| 503 |
|
|
} |
| 504 |
|
|
if (mnem == NULL) |
| 505 |
|
|
break; |
| 506 |
|
|
if (func & 0x80) |
| 507 |
|
|
debug("%s\t%s,0x%x,%s\n", mnem, |
| 508 |
|
|
alpha_regname[ra], (rb << 3) + (func >> 8), |
| 509 |
|
|
alpha_regname[rc]); |
| 510 |
|
|
else |
| 511 |
|
|
debug("%s\t%s,%s,%s\n", mnem, alpha_regname[ra], |
| 512 |
|
|
alpha_regname[rb], alpha_regname[rc]); |
| 513 |
|
|
break; |
| 514 |
|
|
case 0x16: |
| 515 |
|
|
switch (func & 0x7ff) { |
| 516 |
|
|
case 0x080: mnem = "adds"; break; |
| 517 |
|
|
case 0x081: mnem = "subs"; break; |
| 518 |
|
|
case 0x082: mnem = "muls"; break; |
| 519 |
|
|
case 0x083: mnem = "mult"; break; |
| 520 |
|
|
case 0x0a0: mnem = "addt"; break; |
| 521 |
|
|
case 0x0a1: mnem = "subt"; break; |
| 522 |
|
|
case 0x0a2: mnem = "mult"; break; |
| 523 |
|
|
case 0x0a3: mnem = "divt"; break; |
| 524 |
|
|
case 0x0be: mnem = "cvtqt"; rbrc = 1; break; |
| 525 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 526 |
|
|
opcode, func); |
| 527 |
|
|
} |
| 528 |
|
|
if (mnem == NULL) |
| 529 |
|
|
break; |
| 530 |
|
|
if (rbrc) |
| 531 |
|
|
debug("%s\tf%i,f%i\n", mnem, rb, rc); |
| 532 |
|
|
else |
| 533 |
|
|
debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc); |
| 534 |
|
|
break; |
| 535 |
|
|
case 0x17: |
| 536 |
|
|
switch (func & 0x7ff) { |
| 537 |
|
|
case 0x020: mnem = "fabs"; rbrc = 1; break; |
| 538 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 539 |
|
|
opcode, func); |
| 540 |
|
|
} |
| 541 |
|
|
if (mnem == NULL) |
| 542 |
|
|
break; |
| 543 |
|
|
if ((func & 0x7ff) == 0x020 && ra == 31 && rb == 31) |
| 544 |
|
|
debug("fclr\tf%i\n", rc); |
| 545 |
|
|
else if (rbrc) |
| 546 |
|
|
debug("%s\tf%i,f%i\n", mnem, rb, rc); |
| 547 |
|
|
else |
| 548 |
|
|
debug("%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc); |
| 549 |
|
|
break; |
| 550 |
|
|
case 0x18: |
| 551 |
|
|
switch (iw & 0xffff) { |
| 552 |
|
|
case 0x0000: mnem = "trapb"; break; |
| 553 |
|
|
case 0x0400: mnem = "excb"; break; |
| 554 |
|
|
case 0x4000: mnem = "mb"; break; |
| 555 |
|
|
case 0x4400: mnem = "wmb"; break; |
| 556 |
|
|
case 0x8000: mnem = "fetch"; indir = 1; break; |
| 557 |
|
|
case 0xa000: mnem = "fetch_m"; indir = 1; break; |
| 558 |
|
|
case 0xc000: mnem = "rpcc"; break; |
| 559 |
|
|
case 0xe000: mnem = "rc"; break; |
| 560 |
|
|
case 0xe800: mnem = "ecb"; indir = 1; break; |
| 561 |
|
|
case 0xf000: mnem = "rs"; break; |
| 562 |
|
|
case 0xf800: mnem = "wh64"; indir = 1; break; |
| 563 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
| 564 |
|
|
opcode, func); |
| 565 |
|
|
} |
| 566 |
|
|
if (mnem == NULL) |
| 567 |
|
|
break; |
| 568 |
|
|
debug("%s", mnem); |
| 569 |
|
|
if ((iw & 0xffff) >= 0x8000) { |
| 570 |
|
|
debug("\t"); |
| 571 |
|
|
if (indir) |
| 572 |
|
|
debug("(%s)", alpha_regname[rb]); |
| 573 |
|
|
else |
| 574 |
|
|
debug("%s", alpha_regname[ra]); |
| 575 |
|
|
} |
| 576 |
|
|
debug("\n"); |
| 577 |
|
|
break; |
| 578 |
|
|
case 0x1a: |
| 579 |
|
|
tmp = iw & 0x3fff; |
| 580 |
|
|
if (tmp & 0x2000) |
| 581 |
|
|
tmp |= 0xffffffffffffc000ULL; |
| 582 |
|
|
tmp <<= 2; |
| 583 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
| 584 |
|
|
switch ((iw >> 14) & 3) { |
| 585 |
|
|
case 0: |
| 586 |
|
|
case 1: if (((iw >> 14) & 3) == 0) |
| 587 |
|
|
debug("jmp"); |
| 588 |
|
|
else |
| 589 |
|
|
debug("jsr"); |
| 590 |
|
|
debug("\t%s,", alpha_regname[ra]); |
| 591 |
|
|
debug("(%s),", alpha_regname[rb]); |
| 592 |
|
|
debug("0x%llx", (long long)tmp); |
| 593 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 594 |
|
|
tmp, &offset); |
| 595 |
|
|
if (symbol != NULL) |
| 596 |
|
|
debug("\t<%s>", symbol); |
| 597 |
|
|
break; |
| 598 |
|
|
case 2: debug("ret"); |
| 599 |
|
|
break; |
| 600 |
|
|
default:fatal("unimpl JSR!"); |
| 601 |
|
|
} |
| 602 |
|
|
debug("\n"); |
| 603 |
|
|
break; |
| 604 |
|
|
case 0x30: |
| 605 |
|
|
case 0x34: |
| 606 |
|
|
tmp = iw & 0x1fffff; |
| 607 |
|
|
if (tmp & 0x100000) |
| 608 |
|
|
tmp |= 0xffffffffffe00000ULL; |
| 609 |
|
|
tmp <<= 2; |
| 610 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
| 611 |
|
|
debug("%s\t", opcode==0x30? "br" : "bsr"); |
| 612 |
|
|
if (ra != ALPHA_ZERO) |
| 613 |
|
|
debug("%s,", alpha_regname[ra]); |
| 614 |
|
|
debug("0x%llx", (long long)tmp); |
| 615 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 616 |
|
|
tmp, &offset); |
| 617 |
|
|
if (symbol != NULL) |
| 618 |
|
|
debug("\t<%s>", symbol); |
| 619 |
|
|
debug("\n"); |
| 620 |
|
|
break; |
| 621 |
|
|
case 0x38: |
| 622 |
|
|
case 0x39: |
| 623 |
|
|
case 0x3a: |
| 624 |
|
|
case 0x3b: |
| 625 |
|
|
case 0x3c: |
| 626 |
|
|
case 0x3d: |
| 627 |
|
|
case 0x3e: |
| 628 |
|
|
case 0x3f: |
| 629 |
|
|
switch (opcode) { |
| 630 |
|
|
case 0x38: mnem = "blbc"; break; |
| 631 |
|
|
case 0x39: mnem = "beq"; break; |
| 632 |
|
|
case 0x3a: mnem = "blt"; break; |
| 633 |
|
|
case 0x3b: mnem = "ble"; break; |
| 634 |
|
|
case 0x3c: mnem = "blbs"; break; |
| 635 |
|
|
case 0x3d: mnem = "bne"; break; |
| 636 |
|
|
case 0x3e: mnem = "bge"; break; |
| 637 |
|
|
case 0x3f: mnem = "bgt"; break; |
| 638 |
|
|
} |
| 639 |
|
|
tmp = iw & 0x1fffff; |
| 640 |
|
|
if (tmp & 0x100000) |
| 641 |
|
|
tmp |= 0xffffffffffe00000ULL; |
| 642 |
|
|
tmp <<= 2; |
| 643 |
|
|
tmp += dumpaddr + sizeof(uint32_t); |
| 644 |
|
|
debug("%s\t%s,", mnem, alpha_regname[ra]); |
| 645 |
|
|
debug("0x%llx", (long long)tmp); |
| 646 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 647 |
|
|
tmp, &offset); |
| 648 |
|
|
if (symbol != NULL) |
| 649 |
|
|
debug("\t<%s>", symbol); |
| 650 |
|
|
debug("\n"); |
| 651 |
|
|
break; |
| 652 |
|
|
default:debug("UNIMPLEMENTED opcode 0x%x\n", opcode); |
| 653 |
|
|
} |
| 654 |
|
|
|
| 655 |
|
|
return sizeof(uint32_t); |
| 656 |
|
|
} |
| 657 |
|
|
|
| 658 |
|
|
|
| 659 |
|
|
#define MEMORY_RW alpha_userland_memory_rw |
| 660 |
|
|
#define MEM_ALPHA |
| 661 |
|
|
#define MEM_USERLAND |
| 662 |
|
|
#include "../memory_rw.c" |
| 663 |
|
|
#undef MEM_USERLAND |
| 664 |
|
|
#undef MEM_ALPHA |
| 665 |
|
|
#undef MEMORY_RW |
| 666 |
|
|
|
| 667 |
|
|
|
| 668 |
|
|
#include "tmp_alpha_tail.c" |
| 669 |
|
|
|
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