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/* |
/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: bintrans_alpha.c,v 1.1 2005/08/29 14:36:41 debug Exp $ |
* $Id: bintrans_alpha.c,v 1.4 2006/02/09 22:40:26 debug Exp $ |
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* |
* |
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* Alpha specific code for dynamic binary translation. |
* Alpha specific code for dynamic binary translation. |
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* |
* |
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0x86, 0x00, 0x00, 0x00, /* imb */ |
0x86, 0x00, 0x00, 0x00, /* imb */ |
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0x01, 0x80, 0xfa, 0x6b, /* ret */ |
0x01, 0x80, 0xfa, 0x6b, /* ret */ |
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0x1f, 0x04, 0xff, 0x47, /* nop */ |
0x1f, 0x04, 0xff, 0x47, /* nop */ |
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0x00, 0x00, 0xfe, 0x2e, /* unop */ |
0x00, 0x00, 0xfe, 0x2f, /* unop */ |
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0x1f, 0x04, 0xff, 0x47, /* nop */ |
0x1f, 0x04, 0xff, 0x47, /* nop */ |
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0x00, 0x00, 0xfe, 0x2e, /* unop */ |
0x00, 0x00, 0xfe, 0x2f, /* unop */ |
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0x1f, 0x04, 0xff, 0x47, /* nop */ |
0x1f, 0x04, 0xff, 0x47, /* nop */ |
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0x00, 0x00, 0xfe, 0x2e /* unop */ |
0x00, 0x00, 0xfe, 0x2f /* unop */ |
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}; |
}; |
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#define ofs_c0 ((size_t)&dummy_vth32_table.bintrans_chunks[0] - (size_t)&dummy_vth32_table) |
#define ofs_c0 ((size_t)&dummy_vth32_table.bintrans_chunks[0] - (size_t)&dummy_vth32_table) |
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#define ofs_cb (((size_t)&dummy_cpu.cd.mips.chunk_base_address) - (size_t)&dummy_cpu) |
#define ofs_cb (((size_t)&dummy_cpu.cd.mips.chunk_base_address) - (size_t)&dummy_cpu) |
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#define ofs_h_l (((size_t)&dummy_cpu.cd.mips.host_load) - ((size_t)&dummy_cpu)) |
#define ofs_h_l (((size_t)&dummy_cpu.cd.mips.host_OLD_load) - ((size_t)&dummy_cpu)) |
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#define ofs_h_s (((size_t)&dummy_cpu.cd.mips.host_store) - ((size_t)&dummy_cpu)) |
#define ofs_h_s (((size_t)&dummy_cpu.cd.mips.host_OLD_store) - ((size_t)&dummy_cpu)) |
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static uint32_t bintrans_alpha_load_32bit[18] = { |
static uint32_t bintrans_alpha_load_32bit[18] = { |
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0x209f0fff, /* lda t3,4095 */ |
0x209f0fff, /* lda t3,4095 */ |
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0x48419682, /* srl t1,0xc,t1 t1 = addr >> 12 */ |
0x48419682, /* srl t1,0xc,t1 t1 = addr >> 12 */ |
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0x46240004, /* and a1,t3,t3 t3 = addr & 4095 */ |
0x46240004, /* and a1,t3,t3 t3 = addr & 4095 */ |
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0x40580642, /* s8addq t1,t10,t1 &host_load[t1] */ |
0x40580642, /* s8addq t1,t10,t1 &host_OLD_load[t1] */ |
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0xa6620000, /* ldq a3,0(t1) a3 = host_load[t1] */ |
0xa6620000, /* ldq a3,0(t1) a3 = host_OLD_load[t1] */ |
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/* NULL? Then return failure at once. */ |
/* NULL? Then return failure at once. */ |
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0xe6600002, /* beq a3, return */ |
0xe6600002, /* beq a3, return */ |
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0x209f0fff, /* lda t3,4095 */ |
0x209f0fff, /* lda t3,4095 */ |
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0x48419682, /* srl t1,0xc,t1 t1 = addr >> 12 */ |
0x48419682, /* srl t1,0xc,t1 t1 = addr >> 12 */ |
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0x46240004, /* and a1,t3,t3 t3 = addr & 4095 */ |
0x46240004, /* and a1,t3,t3 t3 = addr & 4095 */ |
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0x404f0642, /* s8addq t1,s6,t1 &host_store[t1] */ |
0x404f0642, /* s8addq t1,s6,t1 &host_OLD_store[t1] */ |
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0xa6620000, /* ldq a3,0(t1) a3 = host_store[t1] */ |
0xa6620000, /* ldq a3,0(t1) a3 = host_OLD_store[t1] */ |
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/* NULL? Then return failure at once. */ |
/* NULL? Then return failure at once. */ |
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/* beq a3, return */ |
/* beq a3, return */ |
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/* |
/* |
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* bintrans_backend_init(): |
* bintrans_backend_init(): |
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* |
* |
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* This is neccessary for broken 2.95.4 compilers on FreeBSD/Alpha 4.9, |
* This is necessary for broken 2.95.4 compilers on FreeBSD/Alpha 4.9, and |
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* and probably a few others. (For Compaq's CC, and for gcc 3.x, this |
* probably a few others. (For Compaq's CC, and for gcc 3.x, this wouldn't be |
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* wouldn't be neccessary, and the old code would have worked.) |
* needed; the old code would have worked.) |
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*/ |
*/ |
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static void bintrans_backend_init(void) |
static void bintrans_backend_init(void) |
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{ |
{ |
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*p++ = 0xa5900000 | ofs_ra; /* ldq s3,"gpr[ra]"(a0) */ |
*p++ = 0xa5900000 | ofs_ra; /* ldq s3,"gpr[ra]"(a0) */ |
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*p++ = 0xa5b00000 | ofs_t0; /* ldq s4,"gpr[t0]"(a0) */ |
*p++ = 0xa5b00000 | ofs_t0; /* ldq s4,"gpr[t0]"(a0) */ |
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*p++ = 0xa5d00000 | ofs_t1; /* ldq s5,"gpr[t1]"(a0) */ |
*p++ = 0xa5d00000 | ofs_t1; /* ldq s5,"gpr[t1]"(a0) */ |
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*p++ = 0xa5f00000 | ofs_h_s; /* ldq s6,host_store(a0) */ |
*p++ = 0xa5f00000 | ofs_h_s; /* ldq s6,host_OLD_store(a0) */ |
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*p++ = 0xa7100000 | ofs_h_l; /* ldq t10,host_load(a0) */ |
*p++ = 0xa7100000 | ofs_h_l; /* ldq t10,host_OLD_load(a0) */ |
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*p++ = 0xa7300000 | ofs_v0; /* ldq t11,"gpr[v0]"(a0) */ |
*p++ = 0xa7300000 | ofs_v0; /* ldq t11,"gpr[v0]"(a0) */ |
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*p++ = 0x6b514000; /* jsr ra,(a1),<back> */ |
*p++ = 0x6b514000; /* jsr ra,(a1),<back> */ |