/[gxemul]/trunk/src/cpus/backend_alpha.c
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Contents of /trunk/src/cpus/backend_alpha.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: backend_alpha.c,v 1.2 2005/12/16 21:44:42 debug Exp $
29 *
30 * Dyntrans backend for Alpha hosts.
31 *
32 *
33 * Registers are currently allocated as follows:
34 *
35 * s0 = saved copy of original a0 (struct cpu *)
36 * s1 = saved copy of original t12 (ptr to the function itself)
37 */
38
39 #include <stdio.h>
40 #include <stdlib.h>
41 #include <string.h>
42
43 #include "cpu.h"
44 #include "misc.h"
45
46 #define ALPHA_T0 1
47 #define ALPHA_T1 2
48 #define ALPHA_T2 3
49 #define ALPHA_T3 4
50 #define ALPHA_T4 5
51 #define ALPHA_T5 6
52 #define ALPHA_T6 7
53 #define ALPHA_T7 8
54 #define ALPHA_S0 9
55 #define ALPHA_S1 10
56 #define ALPHA_S2 11
57 #define ALPHA_S3 12
58 #define ALPHA_S4 13
59 #define ALPHA_S5 14
60 #define ALPHA_S6 15
61 #define ALPHA_A0 16
62 #define ALPHA_A1 17
63 #define ALPHA_A2 18
64 #define ALPHA_A3 19
65 #define ALPHA_A4 20
66 #define ALPHA_A5 21
67 #define ALPHA_T8 22
68 #define ALPHA_T9 23
69 #define ALPHA_T10 24
70 #define ALPHA_T11 25
71 #define ALPHA_RA 26
72 #define ALPHA_T12 27
73 #define ALPHA_ZERO 31
74
75
76 uint32_t alpha_imb[8] = {
77 0x00000086, /* imb */
78 0x6bfa8001, /* ret */
79 0x47ff041f, /* nop */
80 0x2ffe0000, /* unop */
81 0x47ff041f, /* nop */
82 0x2ffe0000, /* unop */
83 0x47ff041f, /* nop */
84 0x2ffe0000 /* unop */
85 };
86
87
88 /*
89 * dtb_host_cacheinvalidate():
90 *
91 * Invalidate the host's instruction cache. On Alpha, this is done by
92 * executing an imb instruction. (This invalidates everything, there is no way
93 * to specify which parts of the cache to affect.)
94 *
95 * NOTE: A simple asm("imb"); would be enough here, but not all compilers
96 * have such simple constructs, so an entire function has to be written as
97 * alpha_imb[] above.
98 */
99 void dtb_host_cacheinvalidate(void *p, size_t len)
100 {
101 /* Long form of ``asm("imb");'' */
102 void (*f)(void) = (void *)&alpha_imb[0];
103 f();
104 }
105
106
107 /*
108 * dtb_function_prologue():
109 *
110 * Incoming register values:
111 * a0 = struct cpu *cpu;
112 * a1 = struct xxx_instr_call *ic;
113 * t12 = pointer to the function start itself
114 *
115 * The prologue code does the following:
116 * 1) Save ra, s0, and s1 onto the stack.
117 * 1) s0 = a0, s1 = t12 (save the incoming args for later use)
118 */
119 uint32_t alpha_prologue[6] = {
120 0x23deffe0, /* lda sp,-32(sp) */
121 0xb75e0000, /* stq ra,0(sp) */
122 0xb53e0008, /* stq s0,8(sp) */
123 0xb55e0010, /* stq s1,16(sp) */
124 0x40001400 | (ALPHA_A0 << 21) | ALPHA_S0,
125 0x40001400 | (ALPHA_T12 << 21) | ALPHA_S1
126 };
127 int dtb_function_prologue(struct translation_context *ctx, size_t *sizep)
128 {
129 memcpy((uint32_t *)ctx->p, alpha_prologue, sizeof(alpha_prologue));
130 *sizep = sizeof(alpha_prologue);
131 return 1;
132 }
133
134
135 /*
136 * dtb_function_epilogue():
137 *
138 * The epilogue code does the following:
139 * 1) Load ra, s0, and s1 from the stack.
140 * 2) Return.
141 */
142 int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep)
143 {
144 uint32_t *q = (uint32_t *) ctx->p;
145
146 *q++ = 0xa75e0000; /* ldq ra,0(sp) */
147 *q++ = 0xa53e0008; /* lda s0,8(sp) */
148 *q++ = 0xa55e0010; /* lda s1,16(sp) */
149 *q++ = 0x23de0020; /* lda sp,32(sp) */
150
151 *q++ = 0x6bfa8001; /* ret */
152 if ((((size_t)q) & 0x7) == 4)
153 *q++ = 0x2ffe0000; /* unop */
154 if ((((size_t)q) & 0xf) == 8) {
155 *q++ = 0x47ff041f; /* nop */
156 if ((((size_t)q) & 0x7) == 4)
157 *q++ = 0x2ffe0000; /* unop */
158 }
159
160 *sizep = ((size_t)q - (size_t)ctx->p);
161 return 1;
162 }
163
164
165 /*
166 * dtb_generate_fcall():
167 *
168 * Generates a function call (to a C function).
169 *
170 * (a0 already contains the cpu pointer)
171 * ldq t12,ofs_a(s1) Get the function address and
172 * ldq a1,ofs_b(s1) the xxx_instr_call pointer.
173 * jsr ra,(t12),<nextinstr> Call the function!
174 * mov s0,a0 Restore a0.
175 */
176 int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx,
177 size_t *sizep, size_t f, size_t instr_call_ptr)
178 {
179 uint32_t *q = (uint32_t *) ctx->p;
180
181 cpu_dtb_add_fixup(cpu, 0, q, f);
182 *q++ = 0xa76a0000; /* ldq t12,ofs(s1) */
183
184 cpu_dtb_add_fixup(cpu, 0, q, instr_call_ptr);
185 *q++ = 0xa62a0000; /* ldq a1,ofs(s1) */
186
187 *q++ = 0x6b5b4000; /* jsr ra,(t12),nextinstr */
188 *q++ = 0x47e90410; /* mov s0,a0 */
189
190 *sizep = ((size_t)q - (size_t)ctx->p);
191 return 1;
192 }
193
194
195 /*
196 * dtb_generate_ptr_inc():
197 *
198 * Generates an increment of a pointer (for example cpu->cd.XXX.next_ic).
199 *
200 * NOTE: The syntax for calling this function is something like:
201 *
202 * dtb_generate_ptr_inc(cpu, &cpu->translation_context,
203 * &cpu->cd.arm.next_ic);
204 */
205 int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx,
206 size_t *sizep, void *ptr, int amount)
207 {
208 uint32_t *q = (uint32_t *) ctx->p;
209 ssize_t ofs = (size_t)ptr - (size_t)(void *)cpu;
210
211 if (ofs < 0 || ofs > 0x7fff) {
212 fatal("dtb_generate_ptr_inc(): Huh? ofs=%p\n", (void *)ofs);
213 exit(1);
214 }
215
216 *q++ = 0xa4500000 | ofs; /* ldq t1, ofs(a0) */
217 *q++ = 0x20420000 | amount; /* lda t1, amount(t1) */
218 *q++ = 0xb4500000 | ofs; /* stq t1, ofs(a0) */
219
220 *sizep = ((size_t)q - (size_t)ctx->p);
221 return 1;
222 }
223
224
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