/[gxemul]/trunk/src/cpus/README_DYNTRANS
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/cpus/README_DYNTRANS

Parent Directory Parent Directory | Revision Log Revision Log


Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File size: 2857 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 $Id: README_DYNTRANS,v 1.7 2005/12/09 05:34:20 debug Exp $
2
3 -------------------------------------------------------------------
4
5 PPC optimizations TODO:
6
7 find high-level bottlenecks!
8
9 inline cr0 field calculation
10
11 load/store with r1 as base?
12
13 multiple load/stores in a row (especially with base = r1)
14
15 almost all branches are of the "general" form now, they don't
16 need to be.
17
18 combinations of compare + branch, similar to arm?
19
20 -------------------------------------------------------------------
21
22
23
24 Dyntrans TODO:
25
26 x) Make sure that all of these could work, at least in theory:
27
28 Instruction Word Delay
29 Arch.: length: size: slot:
30 ------ ------- ----- -----
31 Alpha 32-bit 64 no
32 ARM 32-bit, 16-bit (Thumb) 32 no
33 Atmel AVR 16-bit 8 no
34 F-CPU ? ? ?
35 HPPA 32-bit 64/32 yes
36 i960 32-bit + variable 32 ?
37 IA64 128-bit 64 no
38 M68K 16-bit + variable 32 no
39 M88K ? 32 (?) ?
40 MIPS 32-bit, 16-bit (MIPS16) 64/32 yes
41 OpenRISC ? ? ?
42 PC532 ? 32 (?) ?
43 POWER/PPC 32-bit 64/32 no
44 SH 32-bit, 16-bit (SHcompact) 64/32 yes(*)
45 SPARC 32-bit 64/32 yes
46 x86 8-bit + variable 64/32/16 no
47 VAX 8-bit + variable 32 no
48
49 (*) Delay slot in SHcompact?
50
51
52 x) call/return address cache?
53
54 x) instr_call sequence analysis support? (For handtuning combinations.)
55
56 x) opcode statistics support?
57 TODO: is instr_call statistics enough?
58
59 x) load/stores:
60 o) perhaps refactor/reuse common load/store code?
61 o) support for archs that allow transparent
62 unaligned load/stores (ppc, x86 etc)
63 o) alignment checks ==> exceptions
64 o) native byte order ==> faster loads, etc.
65
66 x) actual cache emulation
67
68 x) SMP: detect when an instruction such as ll/sc or cas is used,
69 and "synchronize" approximately the number of executed instructions
70 (or cycles) across all CPUs.
71
72 x) support for variable-length instructions (x86, m68k, i960, ...)
73 Solution: don't increase the next_ic between every
74 instruction, but let each instruction's handler do
75 that for itself.
76 Problem: what about instructions crossing a (virtual)
77 page boundary? They cannot be translated once
78 and for all :( and must be interpreted slowly!
79
80 x) support for THUMB, MIPS16, userland SH (arm, mips, sh)
81
82 x) support for Delay slots! (mips, sparc, hppa, SHcompact?)
83
84 x) various register-window archs (SPARC etc)
85
86 x) Atmel AVR etc?
87
88 x) Alpha: hahaha, zapnot and inserts/extracts don't
89 compile into very nice code :-| fix this
90 Solution: if short assembly language snippets can be
91 compiled on the current host, then compile such snippets
92 for alpha_instr_zapnot etc.
93
94 x) 64-bit virtual memory translation tables (PPC, Alpha, MIPS,
95 HPPA, sh, amd64, etc)
96
97 x) x86: convert to dyntrans. LOTS of stuff to consider.
98
99 x) 88k? vax? pc532? 6502? 6800? etc
100

  ViewVC Help
Powered by ViewVC 1.1.26