/[gxemul]/trunk/src/cpus/README_DYNTRANS
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC revision 38 by dpavlin, Mon Oct 8 16:21:53 2007 UTC
# Line 1  Line 1 
1  $Id: README_DYNTRANS,v 1.12 2006/10/13 05:01:19 debug Exp $  $Id: README_DYNTRANS,v 1.14 2007/04/10 17:26:20 debug Exp $
2    
3    This README is old. Hm.
4    
5    ---------------------
6    
7  Dyntrans TODO:  Dyntrans TODO:
8    
# Line 22  Dyntrans TODO: Line 26  Dyntrans TODO:
26          OpenRISC        ?                               ?               ?          OpenRISC        ?                               ?               ?
27          PC532           ?                               32 (?)          ?          PC532           ?                               32 (?)          ?
28          POWER/PPC       32-bit                          64/32           no          POWER/PPC       32-bit                          64/32           no
29            RCA180x         8-bit                           8-16 (?)        no
30          SH              32-bit, 16-bit (SHcompact)      64/32           yes(*)          SH              32-bit, 16-bit (SHcompact)      64/32           yes(*)
31          SPARC           32-bit                          64/32           yes          SPARC           32-bit                          64/32           yes
32          Transputer      8-bit                           32/16           no          Transputer      8-bit                           32/16           no
# Line 30  Dyntrans TODO: Line 35  Dyntrans TODO:
35    
36          (*) Delay slot in SHcompact?          (*) Delay slot in SHcompact?
37    
   
   x)  instr_call sequence analysis support? (For handtuning combinations.)  
   
   x)  opcode statistics support?  
                 TODO: is instr_call statistics enough?  
   
   x)  load/stores:  
                 o)  perhaps refactor/reuse common load/store code?  
                 o)  support for archs that allow transparent  
                     unaligned load/stores (ppc, x86 etc)  
                 o)  alignment checks ==> exceptions  
                 o)  native byte order ==> faster loads, etc.  
   
   x)  actual cache emulation  
   
   x)  SMP: detect when an instruction such as ll/sc or cas is used,  
             and "synchronize" approximately the number of executed instructions  
             (or cycles) across all CPUs.  
       Problem: devices such as dev_mp don't work well with such a synch.  
                 scheme.  
   
   x)  support for variable-length instructions (x86, m68k, i960, ...)  
                 Current solution: ic->arg[0] contains the length of the  
                                 instruction (in bytes), and next_ic is  
                                 automatically updated.  
                 Problem: what about instructions crossing a (virtual)  
                         page boundary? They cannot be translated once  
                         and for all :( and must be interpreted slowly!  
   
   x)  support for THUMB, MIPS16, userland SH  (arm, mips, sh)  
   
   x)  support for Delay slots!  (mips, sparc, hppa, SHcompact?)  
   
   x)  various register-window archs (SPARC etc)  
   
   x)  Alpha: hahaha, zapnot and inserts/extracts don't  
             compile into very nice code :-|  fix this  
                 Solution: if short assembly language snippets can be  
                 compiled on the current host, then compile such snippets  
                 for alpha_instr_zapnot etc.  
   
   x)  pc532? 6502? 6800? etc  
   
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