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$Id: README_DYNTRANS,v 1.7 2005/12/09 05:34:20 debug Exp $ |
$Id: README_DYNTRANS,v 1.14 2007/04/10 17:26:20 debug Exp $ |
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PPC optimizations TODO: |
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find high-level bottlenecks! |
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inline cr0 field calculation |
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load/store with r1 as base? |
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multiple load/stores in a row (especially with base = r1) |
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almost all branches are of the "general" form now, they don't |
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need to be. |
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combinations of compare + branch, similar to arm? |
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This README is old. Hm. |
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--------------------- |
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Dyntrans TODO: |
Dyntrans TODO: |
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------ ------- ----- ----- |
------ ------- ----- ----- |
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Alpha 32-bit 64 no |
Alpha 32-bit 64 no |
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ARM 32-bit, 16-bit (Thumb) 32 no |
ARM 32-bit, 16-bit (Thumb) 32 no |
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Atmel AVR 16-bit 8 no |
AVR 16-bit + variable 8 no |
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AVR32 16-bit + variable 32 ? |
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F-CPU ? ? ? |
F-CPU ? ? ? |
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H8 16-bit 8/16 no |
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HPPA 32-bit 64/32 yes |
HPPA 32-bit 64/32 yes |
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i960 32-bit + variable 32 ? |
i960 32-bit + variable 32 ? |
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IA64 128-bit 64 no |
IA64 128-bit 64 no |
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M68K 16-bit + variable 32 no |
M68K 16-bit + variable 32 no |
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M88K ? 32 (?) ? |
M88K 32-bit (+var?) 32 ? |
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MIPS 32-bit, 16-bit (MIPS16) 64/32 yes |
MIPS 32-bit, 16-bit (MIPS16) 64/32 yes |
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OpenRISC ? ? ? |
OpenRISC ? ? ? |
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PC532 ? 32 (?) ? |
PC532 ? 32 (?) ? |
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POWER/PPC 32-bit 64/32 no |
POWER/PPC 32-bit 64/32 no |
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RCA180x 8-bit 8-16 (?) no |
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SH 32-bit, 16-bit (SHcompact) 64/32 yes(*) |
SH 32-bit, 16-bit (SHcompact) 64/32 yes(*) |
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SPARC 32-bit 64/32 yes |
SPARC 32-bit 64/32 yes |
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Transputer 8-bit 32/16 no |
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x86 8-bit + variable 64/32/16 no |
x86 8-bit + variable 64/32/16 no |
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VAX 8-bit + variable 32 no |
VAX 8-bit + variable 32 no |
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(*) Delay slot in SHcompact? |
(*) Delay slot in SHcompact? |
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x) call/return address cache? |
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x) instr_call sequence analysis support? (For handtuning combinations.) |
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x) opcode statistics support? |
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TODO: is instr_call statistics enough? |
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x) load/stores: |
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o) perhaps refactor/reuse common load/store code? |
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o) support for archs that allow transparent |
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unaligned load/stores (ppc, x86 etc) |
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o) alignment checks ==> exceptions |
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o) native byte order ==> faster loads, etc. |
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x) actual cache emulation |
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x) SMP: detect when an instruction such as ll/sc or cas is used, |
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and "synchronize" approximately the number of executed instructions |
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(or cycles) across all CPUs. |
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x) support for variable-length instructions (x86, m68k, i960, ...) |
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Solution: don't increase the next_ic between every |
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instruction, but let each instruction's handler do |
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that for itself. |
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Problem: what about instructions crossing a (virtual) |
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page boundary? They cannot be translated once |
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and for all :( and must be interpreted slowly! |
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x) support for THUMB, MIPS16, userland SH (arm, mips, sh) |
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x) support for Delay slots! (mips, sparc, hppa, SHcompact?) |
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x) various register-window archs (SPARC etc) |
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x) Atmel AVR etc? |
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x) Alpha: hahaha, zapnot and inserts/extracts don't |
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compile into very nice code :-| fix this |
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Solution: if short assembly language snippets can be |
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compiled on the current host, then compile such snippets |
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for alpha_instr_zapnot etc. |
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x) 64-bit virtual memory translation tables (PPC, Alpha, MIPS, |
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HPPA, sh, amd64, etc) |
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x) x86: convert to dyntrans. LOTS of stuff to consider. |
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x) 88k? vax? pc532? 6502? 6800? etc |
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